CMOS-Bipolar Darlington device

• US 4,547,791 A
• Filed: 03/22/1982
• Issued: 10/15/1985
• Est. Priority Date: 04/29/1981
• Status: Expired due to Fees

• Current Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Original Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Inventors: Roger, Bernard P., Vertongen, Bernard
• Primary Examiner(s): Larkins, William D.
• Assistant Examiner(s): Fallick, Eric
• Application Number:
  US06/360,291
• Time in Patent Office: 1,303 Days
• Field of Search: 357/43, 357/46, 357/23 VD, 357/42, 357/56, 307/446, 307/570
• US Class Current: 257/370
• CPC Class Codes: H01L 27/0716 in combination with vertical bipolar transistors and diodes, or capacitors, or resistors
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS

Abstract

A semiconductor device having in a semiconductor body a Darlington amplifier comprising a vertical enhancement VMOS-transistor (T₁) as input transistor and a vertical bipolar power transistor (T₂) as output transistor. In order to increase the switching speed, a lateral enhancement MOS transistor (T₃) of complementary conductivity type to the first transistor (T₁) is connected in parallel with the emitter-base junction of the bipolar output transistor (T₂). The gate electrodes of the first and second transistors are interconnected and associated with an input terminal E. Double and treble epitaxial layer structures are disclosed for integrating the device in the semiconductor body. The lateral third transistor (T₃) may be provided either within or outside the area of an epitaxial layer forming the emitter zone of the second transistor (T₂).

Claims

1. A semiconductor device having a semiconductor body comprising a monolithic integrated Darlington circuit having an input first transistor and an output second transistor, said first transistor being formed by a vertical enhancement insulated gate field effect transistor of the VMOST-type, and said second transistor being a vertical bipolar power transistor, characterized in that the device comprises a third transistor formed by a lateral enhancement insulated gate field effect transistor of complementary conductivity type to said first transistor, said third transistor being connected in parallel with an emitter-base junction of said second transistor, and said gate electrodes of said first and third transistors being interconnected, characterized in that said semiconductor body comprises a substrate region of a first conductivity type on which there are successively provided a first epitaxial layer of the opposite second conductivity type and a second epitaxial layer of said first conductivity type, wherein said substrate region forms a drain zone of said first transistor and a collector zone of said second transistor, wherein said first epitaxial layer forms a base zone of said second transistor, and an emitter zone of said second transistor is formed by a part of said second epitaxial layer, said part surrounding a more highly doped surface zone of said first conductivity type, said base zone of said second transistor being connected to the surface by connection zones of said second conductivity type, one of said connection zones surrounding a surface-adjoining source zone of said first conductivity type of said first transistor, wherein a groove intersects said source zone and connection zone and said groove extends into said substrate region, said groove being lined with an insulating layer on which a gate electrode is provided, and wherein said source and drain zones of said third transistor are formed by first and second surface zones of said second conductivity type, said first surface zone adjoining a connection zone.

2. A semiconductor device as claimed in claim 1, characterized in that said third transistor is provided in a part of said second epitaxial layer forming said emitter zone of said second transistor, and wherein the secnd said surface zone of said second conductivity type adjoins said more highly doped surface zone of said first conductivity type.

3. A semiconductor device as claimed in claim 1, characterized in that said third transistor is provided outside said emitter region of said second transistor and is separated therefrom by a connection zone.