System for switching multirate digitized voice and data

• US 4,547,877 A
• Filed: 06/09/1983
• Issued: 10/15/1985
• Est. Priority Date: 06/09/1983
• Status: Expired due to Term

• Current Assignee: Bell Telephone Laboratories, Inc. (Nokia Corporation)
• Original Assignee: AT&T, Inc.
• Inventors: Slana, Matthew F., Lehman, Harvey R.
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): Chin, Wellington
• Application Number:
  US06/502,617
• Time in Patent Office: 859 Days
• Field of Search: 370/58, 370/66, 370/84, 179/2 DP
• US Class Current: 370/381
• CPC Class Codes: H04L 12/52 using time division techniques in digital transmission systems H04L5/22
• CPC Class Codes: H04Q 11/0421 Circuit arrangements therefor
• CPC Class Codes: H04Q 2213/13106 Microprocessor, CPU
• CPC Class Codes: H04Q 2213/13174 Data transmission, file transfer
• CPC Class Codes: H04Q 2213/13292 Time division multiplexing, TDM
• CPC Class Codes: H04Q 2213/13367 Hierarchical multiplexing, add-drop multiplexing

Abstract

A system for efficiently switching time multiplexed digital signals of different bit rates. A switch is described including switch modules each of which can switch data and/or voice 56 kilobit/second (kb) full-rate channels and 2.4 kb, 4.8 kb, and 9.6 kb subrate channels. All signals from incoming channels are stored in a signal memory and are transmitted to outgoing channels under the control of addresses stored in a control memory. The frame offset of each channel with respect to a standard superframe is detected and used to calculate the addresses to be stored in the control memory. Various arrangements are shown to minimize high speed signal and control memory requirements, and to simplify the process of generating control memory contents.

Claims

1. A time division multiplex switching system for switching multirate digitized byte-organized signals from source channels carried on input digital carrier lines to destination channels carried on output digital carrier lines, each of said source channels having a predetermined byte rate, each of said input digital carrier lines carrying a predetermined plurality of full-rate channels, comprising:

means for generating timing signals defining intervals for digital carrier timing;

means responsive to said timing signals for generating sequential address signals;

digital line controller (DLC) means responsive to said timing signals for assembling byte-organized input signals from said input digital carrier lines into DLC output signals and for distributing byte-organized DLC input signals to said output digital carrier lines;

means for determining an indication of the frame offset of signals for each of said source channels with respect to said timing signals;

processor means responsive to said frame offset indications for calculating signal memory addresses;

signal memory means having the capacity to store at least one byte of said byte-organized signals for each source channel for an interval of time defined by the byte rate of the source channel;

control memory means for storing at least one of said calculated signal memory addresses for each source channel in said input digital carrier lines and for generating signal memory addressing signals;

said signal memory means being responsive to said signal memory addressing signals and to said sequential address signals to store successive bytes of said DLC output signals and to generate successive bytes of said DLC input signals.

12. The switching system of claim 1 in which said DLC means is adapted to distribute a plurality of subrate channels operating at two different byte rates into a single full-rate channel on one of said digital carrier output lines.

13. The switching system of claim 12, in which each full-rate channel has an associated stored identity of its subrate byte rate;

in which a selected full-rate channel transmits a first subrate channel operating at a multiple by the byte rate associated with the stored identity corresponding to said selected full-rate channel; and

in which bytes associated with said first subrate channel are transmitted from said signal memory means to said DLC means at a rate which is said multiple of said associated byte rate.

14. The switching system of claim 1 in which said DLC means comprises a plurality of units and in which said control memory means is distributed over said plurality of units.

15. The switching system of claim 1 in which said digital carrier input and output lines are formed into groups in which each of said DLC means, signal memory means, and control memory means is associated with one of said groups, and in which a digital carrier output line from one of said groups is connected to a digital carrier input line to another of said groups.

2. A time division multiplex switching system for switching multirate digitized byte-organized signals from source channels carried on input digital carrier lines to destination channels carried on output digital carrier lines, in which each of said input and output digital carrier lines transmits a predetermined number of full-rate channels, each of said source channels having a predetermined byte rate, comprising:

means for generating timing signals defining intervals for digital carrier timing and defining full-rate channel, frame and partial superframe intervals;

means responsive to said timing signals for generating sequential address signals;

digital line controller (DLC) means responsive to said timing signals for assembling byte-organized input signals from said input digital carrier lines into DLC output signals and for distributing byte-organized DLC input signals to said output digital carrier lines;

signal memory means having the capacity to store at least one byte of said byte-organized signals for each source channel for an interval of time defined by the byte rate of the source channel;

control memory means for storing at least one signal memory address for each source channel in said input digital carrier lines and for generating signal memory addressing signals;

means responsive to said timing signals for achieving frame synchronism of signals on said input digital carrier lines;

means for measuring the magnitudes of frame offset with respect to said timing signals defining intervals for partial superframes for full-rate channels on said input digital carrier lines and for generating frame offset signals representing said magnitudes; and

processor means responsive to said frame offset signals to generate and store said signal memory addresses in said control memory means;

said signal memory means being responsive to said signal memory addressing signals and to said sequential address signals to store successive bytes of said DLC output signals and to generate successive bytes of said DLC input signals.

3. The switching system of claim 2 in which:

said processor means are adapted to generate signal memory addresses adjusted to compensate for said magnitude of frame offset; and

said DLC means are responsive to said DLC input signals generated by said signal storage means in response to said signal memory address signals to distribute said byte-organized DLC input signals synchronized to said timing signals defining partial superframes to said full-rate channels on said output digital lines.

4. The switching system of claim 2 in which said control memory means is responsive to said sequential address signals for generating said signal memory addressing signals.

5. The switching system of claim 4 in which said means for generating sequential address signals further comprises:

means for storing the identity of the subrate of each full-rate channel and for generating a subrate identity output signal each time a byte from the corresponding full-rate channel is to be stored in said signal memory means; and

means responsive to said timing signals and said subrate identity output signals to generate said sequential address signals.

6. The switching system of claim 5 in which said means for generating said sequential address signals further comprises:

means responsive to said timing signals for generating different signals representing current frame count for different partial superframes;

means responsive to said subrate identity output signals for selecting one of said different signals;

means responsive to said timing signals for generating intraframe time signals; and

means for combining said selected one of said different signals with said intraframe time signals.

7. The invention of claim 4 in which said means for generating said sequential address signals comprises:

means for storing the identity of the subrate of each full-rate channel;

storage means for storing sequential address signals;

means for generating different signals representing current frame numbers for different partial superframes;

means responsive to said stored identity for selecting one of said different signals;

means for generating intraframe time signals;

said storage means being responsive to said intraframe time signals and said selected one of said different signals to generate said sequential address signals.

8. The switching system of claim 4 further comprising:

means for storing the identity of the subrate of each full-rate channel; and

in which said means for generating sequential address signals is responsive to said stored identity to generate said sequential address signals.

9. The switching system of claim 4 further comprising:

means for storing the identity of the subrate of each full-rate channel;

means for storing an indication of the frame offset for each full-rate channel; and

in which said means for generating sequential address signals is responsive to said stored identity and said stored indication to generate said sequential address signals.

10. The switching system of claim 4 in which said digital carrier input and output lines are formed into groups in which each of said DLC means, signal memory means, and control memory means is associated with one of said groups, and in which a digital carrier output line from one of said groups is connected to a digital carrier input line to another of said groups.

11. The switching system of claim 2 in which said processor means is further adapted to generate and store at least one first signal memory address and at least one second signal memory address, associated with a first source channel and a second destination channel operating at different byte rates, at locations in said control store means associated with said second and first channels to transmit signals between said first and second channels.

16. In a time-division multiplexed switching system for switching multirate digitized byte-organized signals from source channels carried on input digital carrier lines to destination channels carried on output digital carrier lines, each of said source and destination channels having a predetermined byte rate and each having associated designated time intervals for accessing said channels, each of said input digital carrier lines carrying a predetermined plurality of full-rate channels, a method of switching the signals from a first one of said source subrate channels of said input digital carrier lines to a second one of said destination subrate channels of said output digital carrier lines, said first source and second destination subrate channels operating at a predetermined byte rate, comprising the steps of:

determining the frame offset of signals of said first subrate channel;

calculating an identity of said first subrate channel adjusted for said frame offset;

storing said identity of said first subrate channel at a location associated with the identity of said second subrate channel;

storing an input byte from said first subrate channel at a time designated for accessing said first subrate channel and at a location associated with said identity of said first subrate channel for an interval of time defined by said predetermined byte rate;

reading said identity of said first subrate channel at a time designated for accessing said second subrate channel at said location associated with the identity of said second subrate channel;

reading said input byte stored from said first subrate channel at said location defined by said identity of said first subrate channel; and

transmitting said input byte stored from said first subrate channel to said second subrate channel.

17. The method of claim 16 in which said interval of time defined by said predetermined byte rate is a multiple of the interbyte interval of said predetermined byte rate.

18. The method of claim 16 in which said interval of time defined by said predetermined byte rate is the interbyte interval of said predetermined byte rate.

19. In a time-division multiplexed switching system for switching multirate digitized byte-organized signals from source channels carried on input digital carrier lines to destination channels carried on output digital carrier lines, each of said source and destination channels having a predetermined byte rate and each having associated designated time intervals for accessing said channels, each of said source and destination subrate channels being transmitted on full-rate channels, a method of switching the signals from a first one of said source subrate channels of said input digital carrier lines to a second one of said destination subrate channels of said output digital carrier lines, comprising the steps of:

measuring the frame offset of said first subrate channel;

storing an identity of said first subrate channel, said identity modified in accordance with said frame offset, at a location associated with the identity of said second subrate channel;

storing an input byte from said first subrate channel at a time designated for accessing said first subrate channel and at a location associated with said identity of said first subrate channel for an interval of time equal to the interbyte interval of the predetermined byte rate of said first and second subrate channels;

reading said identity of said first subrate channel at a time designated for accessing said second subrate channel at said location associated with the identity of said second subrate channel;

reading said input byte stored from said first subrate channel at said location defined by said identity of said first subrate channel; and

transmitting said input byte stored from said first subrate channel to said second subrate channel.

20. The method of claim 19 further comprising the step of:

storing an indication of the subrate of each full-rate channel;

and in which said step of storing an input byte from said first subrate channel comprises the steps of;

generating a storage address defined by said identity of said first subrate channel and the stored indication of the subrate of the full-rate channel which transmits said first subrate channel; and

storing an input byte from said first subrate channel at said storage address.

21. The method of claim 19 further comprising the step of:

storing an indication of the subrate of each full-rate channel;

and in which said step of storing an input byte from said first subrate channel comprises the steps of;

generating a plurality of current frame numbers for partial superframes of the switching systems;

accessing the stored indication of the subrate of the full-rate channel which transmits said first subrate channel;

selecting one of said plurality of current frame numbers on the basis of said stored indication of the subrate;

generating a storage address defined by the identity of said first subrate channel and said selected one of said plurality of current frame numbers; and

storing an input byte from said first subrate channel at said storage address.

22. In a time-division multiplexed switching system for switching multirate digitized byte-organized signals from source channels carried on input digital carrier lines to destination channels carried on output digital carrier lines, each of said source and destination channels having a predetermined byte rate and each having associated designated time intervals from accessing said channels, each of said source and destination subrate channels being transmitted on full-rate channels, a method of switching the signals from a first one of said source subrate channels of said input digital carrier lines to a second one of said destination subrate channels of said output digital carrier lines, comprising the steps of:

measuring and storing the frame offset of each full-rate channel;

storing an indication of the subrate of each full-rate channel;

storing the identity of said first subrate channel at a location associated with the identity of said second subrate channel;

accessing said stored indication of the subrate and the frame offset of the full-rate channel which transmits said first subrate channel;

generating a storage address defined by the identity of said first subrate channel and said accessed stored indications;

storing an input byte from said first subrate channel at said storage address at a time designated for accessing said first subrate channel for an interval of time equal to the interbyte interval of the predetermined rate of said first and second subrate channels;

reading said identity of said first subrate channel at a time designated for accessing said second subrate channel at said location associated with the identity of said second subrate channel;

reading said input byte stored from said first subrate channel at said location defined by said identity of said first subrate channel; and

transmitting said input byte stored from said first subrate channel to said second subrate channel.

23. In a time-division multiplexed switching system for switching multirate digitized byte-organized signals from source channels carried on input digital carrier lines to destination channels carried on output digital carrier lines, each of said source and destination channels having a predetermined byte rate and each having associated designated time intervals for accessing said channels, each of said input digital carrier lines carrying a predetermined plurality of full-rate channels, a method of switching the signals from a first one of said source subrate channels of said input digital carrier lines to a second one of said destination subrate channels of said output digital carrier lines, said first source and second destination subrate channels operating at a predetermined byte rate, comprising the steps of:

determining the frame offset of signals of said first subrate channel;

calculating an identity of said first subrate channel adjusted for said frame offset;

storing the identity of said second subrate channel at a location associated with said identity of said first subrate channel;

reading said identity of said second subrate channel at the time designated for accessing said first subrate channel, at said location associated with the identity of said first subrate channel;

storing an input byte from said first subrate channel at said time designated for accessing said first subrate channel and at a location defined by said identity of said second subrate channel for an interval of time defined by said predetermined byte rate;

reading said input byte stored from said first subrate channel at said location defined by said identity of said second subrate channel at the time designated for accessing said second subrate channel; and

transmitting said input byte stored from said first subrate channel to said second subrate channel.

24. The method of claim 23 in which said interval of time defined by said predetermined byte rate is a multiple of the interbyte interval of said predetermined byte rate.

25. The method of claim 23 in which said interval of time defined by said predetermined byte rate is the interbyte interval of said predetermined byte rate.

26. In a time-division multiplexed switching system for switching multirate digitized byte-organized signals from source channels carried on input digital carrier lines to destination channels carried on output digital carrier lines, each of said source and destination channels having a predetermined byte rate and each having associated designated time intervals for accessing said channels, each of said source and destination channels being transmitted on full-rate channels, a method of switching the signals from a first one of said source subrate channels of said input digital carrier lines to a second one of said destination subrate channels of said output digital carrier lines, comprising the steps of:

measuring the frame offset of said second subrate channel;

storing an identity of said second subrate channel, said identity modified in accordance with said frame offset, at a location associated with the identity of said first subrate channel;

reading said identity of said second subrate channel at the time designated for accessing said first subrate channel, at said location associated with the identity of said first subrate channel;

storing an input byte from said first subrate channel at said time designated for accessing said first subrate channel and at a location defined by said identity of said second channel for an interval of time equal to the interbyte interval of the predetermined byte rate of said first and second subrate channels;

reading said input byte stored from said first subrate channel at said location defined by said identity of said second subrate channel at the time designated for accessing said second subrate channel; and

transmitting said input byte stored from said first subrate channel to said second subrate channel.

27. The method of claim 26 further comprising the step of:

storing an indication of the subrate of each full-rate channel;

and in which said step of reading an input byte from said first subrate channel comprises the steps of;

generating a storage address defined by the identity of said second subrate channel and the stored indication of the subrate of the full-rate channel which transmits said second subrate channel; and

reading an input byte from said first subrate channel at said storage address.

28. The method of claim 26 further comprising the step of:

storing an indication of the subrate of each full-rate channel;

and in which said step of reading an input byte from said first subrate channel comprises the steps of;

generating a plurality of current frame numbers for partial superframes of the switching system;

accessing the stored indication of the subrate of the full-rate channel which transmits said second subrate channel;

selecting one of said plurality of current frame numbers on the basis of said stored indication of the subrate;

generating a storage address defined by the identity of said second subrate channel and said selected one of said plurality of current frame numbers; and

reading an input byte from said first subrate channel at said storage address.

29. In a time-division multiplexed switching system for switching multirate digitized byte-organized signals from source channels carried on input digital carrier lines to destination channels carried on output digital carrier lines, each of said source and destination channels having a predetermined byte rate and each having associated designated time intervals for accessing said channels, each of said source and destination channels being transmitted on full-rate channels, a method of switching the signals from a first one of said source subrate channels of said input digital carrier lines to a second one of said destination subrate channels of said output digital carrier lines, comprising the steps of:

storing an indication of the subrate of each full-rate channel;

measuring and storing an indication of frame offset of each full-rate channel;

storing the identity of said second subrate channel at a location associated with the identity of said first subrate channel;

reading said identity of said second subrate channel at the time designated for accessing said first subrate channel, at said location associated with the identity of said first subrate channel;

storing an input byte from said first subrate channel at said time designated for accessing said first subrate channel and at a location defined by said identity of said second subrate channel for an interval of time equal to the interbyte interval of the predetermined byte rate of said first and second subrate channels;

accessing said stored indication of the subrate and the frame offset of the full-rate channel which transmits said second subrate channel;

generating a storage address defined by the identity of said second subrate channel and said accessed stored indications;

reading an input byte from said first subrate channel at said storage address at a time designated for accessing said second subrate channel; and

transmitting said input byte stored from said first subrate channel to said second subrate channel.

30. A time division multiplex switching system for switching multirate digitized byte-organized signals from one source channel carried on one input digital carrier line to a plurality of destination channels carried on output digital carrier lines, said source channel having a predetermined byte rate, comprising:

means for generating timing signals defining intervals for digital carrier timing;

means responsive to said timing signals for generating sequential address signals;

digital line controller (DLC) means responsive to said timing signals for assembling byte-organized input signals from said input digital carrier line into DLC output signals and for distributing byte-organized DLC input signals to said plurality of destination channels on said output digital carrier lines;

signal memory means having the capacity to store at least one byte of said byte-organized signals for said source channel for an interval of time defined by the byte rate of the source channel;

control memory means for storing at least one signal memory address for each of said plurality of destination channels in said output digital carrier lines and for generating signal memory addressing signals;

said signal memory means being responsive to said signal memory addressing signals and to said sequential address signals to store successive bytes of said DLC output signals and to generate successive bytes of said DLC input signals.