Detector array module-structure and fabrication

• US 4,551,629 A
• Filed: 01/23/1984
• Issued: 11/05/1985
• Est. Priority Date: 09/16/1980
• Status: Expired due to Term

• Current Assignee: Irvine Sensors Corp.
• Original Assignee: Irvine Sensors Corp.
• Inventors: Carson, John C., Clark, Stewart A.
• Primary Examiner(s): Gron, Teddy S.
• Assistant Examiner(s): Locker, Howard J.
• Application Number:
  US06/572,802
• Time in Patent Office: 652 Days
• Field of Search: 29/572, 29/576 J, 29/576 S, 29/590, 29/591, 29/577 C, 156/630, 156/632, 156/636, 156/633, 156/645, 156/646, 250/578, 250/553, 357/75, 422/186
• US Class Current: 250/208.2
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/06555 Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 25/042 the devices being arranged next to each other solar cells H01L31/042
• CPC Class Codes: H01L 25/043 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A photo detector array module is disclosed which comprises a stack of semiconductor chips having integrated circuitry on each chip. To permit the emplacement of photo-detectors on the focal plane end, and of thin film circuitry on the back plane end, each plane is etched to cut back the semiconductor material, then covered with passivation material, and thereafter lapped to uncover the ends of electrical leads on the chips.

Claims

1. A photo-detector array module comprising:

a plurality of integrated-circuit-providing semiconductor substrates of substantially identical dimensions stacked and secured together to form a multiple layer structure, one end of which terminates in a focal plane and the other end of which terminates in a back plane, the semiconductor substrates extending in layers perpendicular to the focal plane and back plane;

the focal plane end of each substrate having thereon a multiplicity of closely spaced electrical contact points provided by the ends of the metal leads formed as part of the integrated circuitry on the substrate, the electrical contact points on the focal plane end of each semiconductor substrate having a predetermined substantially exact spatial relationship with the electrical contact points on the focal plane end of the other stacked semiconductor substrates;

insulation layers between adjacent substrates to insulate the body of each substrate from adjacent substrates in the stack;

insulation covering the entire focal plane end of the stacked substrates except for the contact points thereon, and preventing current leakage between the contact points and the focal plane ends of the substrates;

the back plane end of each substrate having a multiplicity of electrical contact points thereon; and

insulation covering the back plane end of the stacked substrates except for the contact points thereon, and preventing current leakage between the contact points and the back plane ends of the substrates.

2. The photo-detector array module of claim 1 which also includes:

a plurality of electrical conductors formed as stripes on the back plane of the stack of semiconductor chips, each such conductor stripes interconnecting the contact points on a plurality of substrates and providing electrical connections to external wiring.

3. The photo-detector array module of claim 1 which also includes:

a multiplicity of photo-detectors formed independently of the semiconductor substrates and bonded to the focal plane end of the stacked substrates, with each photo-detector in individual electrical contact with a single electrical contact point on the focal plane.

4. The photo-detector array module of either claim 1 or claim 3 wherein the focal plane end of the stacked substrates is prepared by a method including the following steps:

etching the focal plane to remove a thin layer of semiconductor substrate material without affecting the electrical contact points on the focal plane;

applying insulation material to cover the etched surface; and

removing sufficient insulation material from the surface to uncover the electrical contact points.

5. The photo-detector array module of claim 2 wherein the electrical conductor stripes formed on the back plane extend on both sides of each intersecting contact point to provide a T-shaped joint of continuous conductive material.

6. The photo-detector array module of claim 2 or claim 5 wherein the method of providing electrical conductor stripes on the back plane includes the following steps:

etching the back plane to remove a thin layer of semiconductor substrate material without affecting the electrical contact points on the back plane;

applying insulation material to cover the etched surface;

removing sufficient material from the surface to uncover the electrical contact points; and

depositing the electrical conductor stripes by thin film photo-delineation techniques, each conductor stripe being so located as to make electrical contact with the appropriate electrical contact points.

7. A module, wich contains densely-packed electronic components and which is adapted to carry on a front planar supporting surface an array of closely spaced electro-optical electronic-radiative energy conversion elements, comprising:

a plurality of integrated-circuit-providing semiconductor substrates of substantially identical dimensions stacked and secured together to form a multiple layer structure, one end of which terminates in a front plane and the other end of which terminates in a back plane, the semiconductor substrates extending in layers perpendicular to the front plane and back plane;

the front plane end of each substrate having thereon a multiplicity of closely spaced electrical contact points provided by the ends of the metal leads formed as part of the integrated circuitry on the substrate, the electrical contact points on the front plane end of each semiconductor substrate having a predetermined substantially exact spatial relationship with the electrical contact points on the front plane end of the other stacked semiconductor substrates;

insulation layers between adjacent substrates to insulate the body of each substrate from adjacent substrates in the stack;

insulation covering the entire front plane end of the stacked substrates except for the contact points thereon, and preventing current leakage between the contact points and the front plane ends of the substrates;

the back plane end of each substrate having a multiplicity of electrical contact points thereon; and

insulation covering the back plane end of the stacked substrates except for the contact points thereon, and preventing current leakage between the contact points and the back plane ends of the substrates.

8. The module of claim 7 wherein the front planar supporting surface provided by the stacked substrates is prepared by a method including the following steps:

etching the front plane to remove a thin layer of semiconductor substrate material without affecting the electrical contact points on the front plane;

applying insulation material to cover the etched surface; and

removing sufficient insulation material from the surface to uncover the electrical contact points.