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Packet switching system

  • US 4,551,720 A
  • Filed: 03/25/1983
  • Issued: 11/05/1985
  • Est. Priority Date: 03/25/1983
  • Status: Expired due to Fees
First Claim
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1. A real time packet switching system for serially transmitting a matrix of data bytes along a transmission means, the matrix having at least one matrix dimension, comprising:

  • an encoding means comprising;

    means for selecting a set of data bytes having one common matrix dimension, each data byte having a plurality of data bits;

    parallel outputting the data bits of one sequentially selected data byte in said set during each of a plurality of time intervals;

    generating at least one address byte identifying the common dimension and consecutive shifting each of the at least one address byte after all of the data bytes have been sequentially shifted, the set of data bytes and the identifying address bytes defining a word packet; and

    generating a steering signal indicative of whether the address byte is the last to occur address byte in the word packet;

    latch register means for receiving one of the data/address bytes and the steering signal during one of the time intervals and forming a word which comprises a data word when the word includes an address byte, and a steering bit set to correspond to the steering signal valve, andmeans for serially shifting the formed word from the latch register means to the transmission means at a predefined bit rate during the time period between the predefined intervals and serially transmitting the word along the transmission means at the bit rate; and

    decoding means comprising;

    means for detecting the start of each word appearing on the transmission means,register means having a number of storage locations equivalent to the sum of all the bits in the address bytes,means for enabling bit-by-bit serial shifting of just the data and address bytes of the formed word into the register means,means for sensing the level of the steering bit and using the data in the shift register to generate an address command when the steering bit is at a first level indicating that the data in the shift register comprises the at least one address byte.

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