Variable-length encoding-decoding system

• US 4,553,130 A
• Filed: 03/06/1984
• Issued: 11/12/1985
• Est. Priority Date: 03/11/1983
• Status: Expired due to Term

• Current Assignee: Tokyo Shibaura Denki Kabushiki Kaisha (Toshiba Corporation)
• Original Assignee: Tokyo Shibaura Denki Kabushiki Kaisha (Toshiba Corporation)
• Inventors: Kato, Masaaki
• Primary Examiner(s): Shoop, Jr., William M.
• Assistant Examiner(s): Logan, Sharon D.
• Application Number:
  US06/586,743
• Time in Patent Office: 616 Days
• Field of Search: 340/347 DD
• US Class Current: 341/67
• CPC Class Codes: G11B 20/1426 conversion to or from block codes or representations thereof
• CPC Class Codes: H03M 7/40 Conversion to or from variable length codes, e.g. Shannon-Fano code, Huffman code, Morse code

Abstract

A variable-length encoding device includes a shift register for converting a binary data string representing an audio signal into unit words of three 2-bit data (e.g., (1,1), (1,0), and (0,1) and two 3-bit data (e.g., (0,0,0) and (0,0,1). The 3-bit data words are obtained such that the remaining 2-bit data (i.e., (0,0)) is used as upper two bits of each of the resultant 3-bit data and is combined with each of the "1" and "0" data of the resultant 3-bit data. The output data words from the shift register are converted by a logic circuit to the corresponding code words in one-to-one correspondence. Each code word has a bit number twice that of the input data word. If a bit array (1,0,1) is included in the code word bit stream thus obtained, this bit array is further converted to (0,0,1).

Claims

1. A variable-length encoding method comprising the steps of:

(a) receiving a binary digital data stream and framing the binary digital data string by using as a unit word any one of three 2-bit data and two 3-bit data in accordance with a state of said digital data string, said 2-bit data being three data words constituted by a first combination of three 2-bit data selected from a second combination of four 2-bit data (0,0), (0,1), (1,0) and (1,1), said 3-bit data being data words produced such that a remaining one of said second combination is used as upper bits of each of said 3-bit data and is combined with each of two 1-bit data as a lower bit of said 3-bit data;

(b) sequentially receiving said data words, converting each one of the data words such that a given data word of said data words which is to be encoded is encoded to a corresponding one of 4-bit code words when the given data word corresponds to one of the 2-bit data, and the given data word is encoded to a corresponding one of 6-bit code words when the given data word corresponds to one of the 3-bit data, and producing a code word string;

(c) further encoding a specific data array (1,0,1) to (0,0,1) when the specific data array is included in a code word of the code word string; and

(d) producing a recording signal which has a pulse waveform subjected to alternate transition between first and second signal levels so as to correspond to positions of logic "1" data of an obtained data string of the code word string, and recording the recording signal on a recording medium.

2. The method according to claim 1, wherein the code words comprise:

three 4-bit code words (0,1,0,0), (0,0,Y,0) and (1,0,0,0) respectively corresponding to the three 2-bit data words; and

two 6-bit code words (0,0,0,1,0,0) and (1,0,0,1,0,0,) respectively corresponding to the two 3-bit data words, where a bit signal Y represents a bit value such that Y=0 when another code word following a code word including the bit signal Y has an MSB of logic "1" and Y=1 when the MSB is set to be logic "0".

3. The method according to claim 1, wherein the code words comprise:

three 4-bit code words (0,1,0,0), (0,0,1,0) and (1,0,0,0) respectively corresponding to the three 2-bit data words; and

two 6-bit code words (0,0,0,1,0,0) and (1,0,0,1,0,0,) respectively corresponding to the two 3-bit data words.

4. The method according to claim 3, wherein an upper third bit of logic "1" of the code word (0,0,1,0) as one of the three 4-bit code words is further encoded to be logic "0" when the most significant bit of another code word following the code word (0,0,1,0) is set to be logic "1", whereby two "0"s are normally inserted between two nearest adjacent "1"s of the code word bit stream obtained by said encoding method.

5. The method according to claim 4, wherein an upper fourth bit of each of said code words is set to be normally "0" in the 4-bit code words and "1" in the 6-bit code words, whereby the upper fourth bit data is used as a marker bit to detect whether the given word corresponds to one of the 4 and 6-bit code words when the given word is decoded in a reproduction mode of the recording signal.

6. A variable-length encoding system comprising:

(a) data word generator means for receiving a binary digital data stream and for framing the binary digital data stream by using as a unit word a data word of variable length in accordance with a state of the data string, thereby generating a data word string, said data word of variable length being any one of three 2-bit data and two 3-bit data in accordance with the state of said digital data string, said 2-bit data being first three data words constituted by a first combination of three 2-bit data selected from a second combination of four 2-bit data (0,0), (0,1), (1,0) and (1,1), said 3-bit data being second data words produced such that a remaining one of said second combination is used as upper bits of each of said 3-bit data and is combined with each of two 1-bit data as a lower bit of said 3-bit data;

(b) first logic circuit means, connected to said data word generator means, for sequentially receiving the data words and performing a predetermined logic operation for converting each one of the data words such that a given data word of said data words which is subjected to encoding is encoded to a corresponding one of 4-bit code words when the given data word corresponds to one of the 2-bit data, and the given data word is encoded to a corresponding one of 6-bit code words when the given data word corresponds to one of the 3-bit data, and producing a code word string;

(c) second logic circuit means, connected to said first logic circuit means, for detecting a specific data array (1,0,1) included in the code words generated from said first logic circuit means and converting the specific data array to another data array; and

(d) flip-flop circuit means, connected to said second logic circuit means, for producing a recording signal which has a waveform subjected to alternate transition between first and second signal levels in correspondence to positions of logic "1" data in a code word bit of stream and which is directly recorded on a predetermined magnetic recording medium.

7. The system according to claim 6, wherein said first logic circuit means converts a currently received data word of said data words to any one of the 4-bit code words (0,1,0,0), (0,0,1,0) and (1,0,0,0) in one-to-one correspondence when the currently received data word is one of the three 2-bit data.

8. The system according to claim 7, wherein said first logic circuit means converts a currently received data word of said data words to any one of the 6-bit code words (0,0,0,1,0,0) and (1,0,0,1,0,0) in one-to-one correspondence when the currently received data word is one of the two 3-bit data.

9. The system according to claim 8, wherein said second logic circuit means changes an upper third bit of the 4-bit code word (0,0,1,0) in accordance with a state of a code word generated next to the code word (0,0,1,0) when the 4-bit code word (0,0,1,0) is generated from said first logic circuit means.

10. The system according to claim 9, wherein said second logic circuit means comprises means for inverting the upper third bit of logic "1" of the 4-bit code word (0,0,1,0) to data of logic "0" when the code word next to the code word (0,0,1,0) has an MSB of logic "1".