Latching comparator with hysteresis

• US 4,554,468 A
• Filed: 07/01/1983
• Issued: 11/19/1985
• Est. Priority Date: 07/01/1983
• Status: Expired due to Fees

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Miller, Ira, Rumbaugh, Robert C.
• Primary Examiner(s): Zazworsky, John
• Application Number:
  US06/510,044
• Time in Patent Office: 872 Days
• Field of Search: 307/355, 307/356, 307/530, 307/362, 307/288
• US Class Current: 327/66
• CPC Class Codes: H03K 3/2897 with an input circuit of differential configuration

Abstract

A self latching comparator circuit has upper and lower input offset voltages associated therewith to establish hysteresis in response to a differential input signal. The comparator circuit comprises a differential amplifier adapted to receive a differential input signal and first and second parallel current mirror circuits for producing upper and lower input offset voltages when each are respectively activated. Antisaturation means are provided for preventing the current mirror circuits from saturating. An output circuit is also provided which does not load the differential output and therefore provides for a well controlled hysteresis.

Claims

1. A self latching comparator circuit having hysteresis, comprising:

differential amplifier means having first and second inputs and first and second outputs, said first and second inputs being responsive to a differential signal applied thereacross;

first current mirror means coupled to said first and second outputs for producing a first predetermined input offset voltage in said differential amplifier means when said first current mirror means is activated, said first current mirror means including first transistor means;

second current mirror means coupled between said first and second outputs and a common node for producing a second predetermined input offset voltage in said differential amplifier means when said second current mirror means is activated, said second current mirror means being activated when the magnitude of said differential input signal incrementally exceeds said first predetermined input offset voltage in a positive sense for regeneratively inactivating said first current mirror means and said first current mirror means being activated when the magnitude of the differential input signal incrementally exceeds said second input offset voltage in a negative sense for regeneratively inactivating said second current mirror means, said second current mirror means including second transistor means;

first means for preventing said first transistor means from saturating when said first current mirror means is activated;

second means for preventing said second transistor means from saturating when said second current mirror means is activated; and

output circuit means coupled to said common node for causing a voltage level at an output thereof to switch between first and second output level states after said first and second current mirror means are respectively activated.

2. A circuit according to claim 1 wherein said first current mirror means includes:

first diode means coupled between said first output and a first source of supply voltage, said first transistor means having base, emitter and collector terminals, said emitter terminal coupled to said first source of supply voltage, said collector terminal coupled to said second output, and said base terminal coupled to said first diode means.

3. The circuit according to claim 2 wherein said second current mirror means includes second diode means coupled between said second output and said first source of supply voltage, said second transistor means having base, emitter and collector terminals, said collector terminal coupled to said first output, said emitter terminal coupled to said first source of supply voltage and said base terminal coupled to said second diode means.

4. A circuit according to claim 3 wherein said first diode means includes third transistor means having base, emitter and collector terminals, said emitter terminal being coupled to said first source of supply voltage, and said base terminal and collector terminal being coupled to said first output and to the base terminal of said first transistor means, the emitter area of said first transistor means being N times greater than the emitter area of said third transistor means.

5. A comparator circuit according to claim 4 wherein said second diode means includes fourth transistor means having base, emitter and collector terminals, said emitter terminal coupled to said first source of supply voltage, and said base and collector terminals being coupled to said second output and to the base terminal of said second transistor means, the emitter area of said second transistor means being N'"'"' times greater than the emitter area of said fourth transistor means.

6. A comparator circuit according to claim 5 wherein said first means comprises fifth transistor means having base, emitter and collector terminals, said base and collector terminals being coupled to said first output and said emitter terminal being coupled to said second output.

7. A circuit according to claim 6 wherein said second means comprises sixth transistor means having base, emitter and collector terminals, said base and collector terminals being coupled to said second output and the emitter terminal being coupled to said first output.

8. A compprator circuit according to claim 5 wherein said first means comprises a dual emitter transistor having base and collector terminals coupled to said first output, having a first emitter terminal coupled to said second output, and a second emitter terminal coupled to the base terminal of said third transistor means.

9. The circuit according to claim 8 wherein said second means comprises a dual emitter transistor having base and collector terminals coupled to said second output, a first emitter terminal coupled to said first output and a second emitter terminal coupled to the base of said fourth transistor means.