Memory utilization control system for compressed digital picture data transmission system

• US 4,554,597 A
• Filed: 11/03/1983
• Issued: 11/19/1985
• Est. Priority Date: 11/05/1982
• Status: Expired due to Fees

• Current Assignee: Victor Company of Japan Limited (JVC Kenwood Corporation)
• Original Assignee: Victor Company of Japan Limited (JVC Kenwood Corporation)
• Inventors: Tanaka, Koji, Sugiyama, Hiroyuki, Sato, Hideo, Kubo, Mitsuo, Furuki, Tsuneo, Shibamoto, Takeshi
• Primary Examiner(s): MCELHENY JR, DONALD E
• Application Number:
  US06/548,415
• Time in Patent Office: 747 Days
• Field of Search: 358/335, 358/339, 358/324, 358/310, 358/312, 358/313, 358/342, 358/907, 358/140, 358/11, 358/141, 360/10.1, 360/10.2, 360/10.3, 360/11.1
• US Class Current: 386/341
• CPC Class Codes: H04N 1/2112 using still video cameras
• CPC Class Codes: H04N 1/2141 in a multi-frame buffer
• CPC Class Codes: H04N 2101/00 Still video cameras
• CPC Class Codes: H04N 9/8066 with insertion of the PCM audio signals in the vertical blanking interval of the PCM video signal
• CPC Class Codes: H04N 9/877 by assembling picture element blocks in an intermediate memory

Abstract

An improved memory utilization control system for compressed digital picture data transmission systems, comprises an input terminal coupled to the memory circuit having a capacity of one frame, an address signal generator generating an address signal which successively indicates write-in addresses in first and second memory regions each amounting to one field in the memory circuit when picture element data of frame-transmission to be reproduced in the first and second fields are applied to the input terminal, and for generating two address signals which respectively and successively indicate write-in addresses in the first and second memory regions when picture element data of field-transmission are applied to the input terminal, a write-in pulse generator generating write-in pulses for writing the picture element data into the memory circuit, and a read-out control circuit for reading out stored picture element data from the first memory region during reproduction of the first field, and for reading out stored picture element data from the second memory region during reproduction of the second field, so that a total capacity of the memory circuit required otherwise is reduced drastically.

Claims

1. A write-in and read-out control apparatus for controlling write-in and read-out of picture element data with respect to a memory circuit, said memory circuit having a memory capacity capable of storing picture element data amounting to one frame and being selectively supplied with picture element data of frame-transmission and picture element data of field-transmission, said frame-transmission being a transmission of all picture element data which are related to a displaying area within a total display area of one picture, said picture element data of frame-transmission amounting to one frame or less according to the size of said displaying area with respect to said total display area, said field-transmission being a transmission of half of the picture element data which are related to the displaying area within the total display area of said one picture, said picture element data of field-transmission amounting to one field or less according to the size of said displaying area with respect to said total display area, said write-in and read-out control apparatus comprising:

input terminal means successively applied with input picture element data, said input terminal means being coupled to said memory circuit;

an address signal generating means for generating an address signal which successively indicates write-in addresses in a first memory region corresponding to one field within said memory circuit into which picture element data which are to be reproduced in a first field among said input picture element data are written, and generating an address signal which successively indicates write-in addresses in a second memory region corresponding to one field within said memory circuit into which picture element data which are to be reproduced in a second field are written, when said picture element data of frame-transmission are successively applied to said input terminal means as said input picture element data, and for generating two address signals which respectively and successively indicate write-in addresses in the first and second memory regions into which said picture element data of field-transmission are written, when said picture element data of field-transmission are successively applied to said input terminal means as said input picture element data;

write-in pulse generating means for generating at least one write-in pulse when said picture element data of frame-transmission are successively applied to said input terminal means every time one of said input picture element data is applied to said input terminal means, to supply the generated write-in pulse to said memory circuit and write said input picture element data into said memory circuit, and for generating one or two write-in pulses when said picture element data of field-transmission are successively applied to said input terminal means every time one of said input picture element data is applied to said input terminal means, to supply the generated write-in pulse or pulses to said memory circuit and write said input picture element data into said memory circuit; and

read-out control means for generating a read-out address signal and supplying the generated read-out address signal to said memory circuit, said read-out address indicating an address which is incremented by a predetermined integer regardless of whether stored picture element data in said memory circuit are picture element data of frame-transmission or field-transmission, so that the stored picture element data are read out from said first memory region during a reproducing period of the first field and so that the stored picture element data are read out from said second memory region during a reproducing period of the second field.

2. A write-in and read-out control apparatus as claimed in claim 1 in which said picture element data of frame transmission are successively transmitted time-divisionally in a sequence such that picture element data arranged in vertical columns in a picture are transmitted horizontally, said address signal generating means generates a write-in address signal indicating an address which is incremented by a predetermined integer every time two picture element data which are displayed at the same vertical location in the picture are applied to said input terminal means, and said two picture element data are written at the same address in each of said first and second memory regions within said memory circuit.

3. A write-in and read-out control apparatus as claimed in claim 1 in which said picture element data of field-transmission are picture element data which are to be arranged in a checkered pattern among picture element data which are arranged in a matrix pattern and make up one picture.

4. A write-in and read-out control apparatus as claimed in claim 1 in which said picture element data of field-transmission are picture element data which are to be arranged in a checkered pattern among picture element data which are arranged in a matrix pattern and make up one picture, and are successively transmitted time-divisionally in a sequence such that picture element data arranged in vertical columns in a picture are transmitted horizontally, said address signal generating means comprises first and second address counters which respectively generate write-in address signals indicating addresses which mutually differ by a predetermined integer and are respectively incremented by a predetermined integer every time a picture element data is applied ro said input terminal means, and means for supplying said write-in address signal generated from said first and second address counters to said memory circuit, said write-in pulse generating means generates a write-in pulse so that only a first picture element data among picture element data displayed at the same vertical locations in the picture is written into said first memory region according to the write-in address signal from said first address counter when picture element data in odd vertical columns and related to the first field are applied to said input terminal means and so that a second and subsequent picture element data are simultaneously written into said first and second memory regions according to the address signals from said first and second address counters, and generates a write-in pulse so that picture element data in even vertical columns and related to the second field are simultaneously written into said first and second memory regions according to the address signals from said first and second address counters when the picture element data in the even vertical columns and related to the second field are applied to said input terminal means.

5. A write-in and read-out control apparatus as claimed in claim 1 in which said picture element data of frame-transmission and said picture element data of field-transmission which are supplied to said memory circuit, are signals reproduced from the same recording medium.