Method for generating an optimized nested arrangement of constrained rectangles

• US 4,554,625 A
• Filed: 06/14/1983
• Issued: 11/19/1985
• Est. Priority Date: 06/14/1983
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Otten, Ralph H. J. M.
• Primary Examiner(s): Smith, Jerry
• Assistant Examiner(s): MACDONALD, ALLEN R
• Application Number:
  US06/504,206
• Time in Patent Office: 889 Days
• Field of Search: 364/148, 364/475, 364/490, 364/491
• US Class Current: 700/171
• CPC Class Codes: B23D 15/06 Sheet shears B23D15/002 and B23D15/005 take precedence
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06T 17/00 Three dimensional [3D] modelling, e.g. data description of 3D objects
• CPC Class Codes: Y10S 706/908 Electronic or computer, internal or network, circuit

Abstract

The overall arrangement of a number of non-overlapping rectangles with constraints on their size and shape, may be generated with relation to a number of objective functions such as, size and shape of the enveloping rectangle, size of an interconnecting network, and distance between pairs of individual rectangles, by first embedding a distance space, reflecting the desired proximity structure, in the plane; next, by refining containment relations, fixing the relative positions of rectangles within such a containment in accordance with the corresponding positions in the embedding; and on the basis thereof estimating the space required for the local realization of the interconnecting network in a configuration satisfying the constraints on the individual rectangles, and optimal with respect to any quasi-concave objective function on the dimensions of the enveloping rectangle that is monotone in its arguments. The method can be implemented even on relatively small computers. Its major application is in the generation of mask patterns of complex semiconductor integrated circuits, especially when a given functional structure must be preserved by containment in rectangles.

Claims

1. A method for allocating rectangular areas for given elements on a rectangular surface of a product such as an integrated circuit, each element being limited by a shape constraint and related to the other elements by proximity information, comprising the steps of:

deriving a distance space to position a center of each said element on said product surface in a configuration of points in a plane;

constructing a slicing structure from said point configuration of said element centers;

determining from the result of the above steps the dimensions, position, and orientation of said elements; and

dividing up said product surface accordingly.

2. A method according to claim 1, wherein said proximity information comprises:

an interconnection count.

3. A method according to claim 1, wherein said proximity information comprises:

a distance matrix.

4. A method according to claim 1, wherein said proximity information comprises:

a weights matrix.

5. A method according to claim 1, wherein said proximity information comprises:

a wiring net list.

6. A method according to claim 5, wherein individual weights are assigned to the nets in said wiring net list.

7. A method according to claim 1, wherein said proximity information comprises:

an incidence structure over said elements and interrelations.

8. A method according to claim 7, wherein individual weights are assigned to the interrelations of said incidence structure.

9. A method according to claim 1, wherein said proximity information leads to a configuration of points in the plane, where the points represent said elements.

10. A method according to claim 1, wherein said proximity information is a point configuration in the plane.

11. A method according to claim 1, wherein said construction of the slicing structure from the configuration of element centers is based on shrink factors for lines dividing a set of rectangles into disjunct subsets of rectangles without changing their relative position in the perpendicular direction.

12. A method according to claim 1, wherein said construction of the slicing structure from the configuration of element centers is based on the deformation the elements will incur if a set of lines is accepted as the next set of slicing lines.

13. A method according to claim 1, wherein said construction of the slicing structure from the configuration of element centers is based on the distribution of area over the ensuing slices after accepting a set of lines as the next set of slicing lines.

14. A method according to claim 1, wherein said construction of the slicing structure is based on determining the geometry of the partial slicing structure with all elements considered to be flexible and all interspaces assumed to be zero.

15. A method according to claim 1, wherein said construction of the slicing structure is based on a combination of at least two of the following indicators:

shrink factors, deformation, area distribution, and geometrical top-down calculations under the assumption of only flexible elements and no interspaces.

16. A method according to claim 1, comprising the further step of:

determining the distances required between elements for the realization of the interrelations among the elements.

17. A method according to claim 24 wherein said distances needed for realizing the interrelations among the elements are assumed to be located between consecutive sibling slices, in junction cells.

18. A method according to claim 17, wherein said determining of the distances needed for realizing the interrelations consists of assessing the latitudinal dimensions of the junction cells.

19. A method according to claim 18, wherein said assessing of the latitudinal dimensions of the junction cells is based on the assignment of nets to the junction cell segments between consecutive junction cell intersections.

20. A method according to claim 19, wherein said assignment of the nets to the junction cell segments between consecutive junction cell intersections is based on solving the Steiner problem on the junction cell intersection structure, using the slicing properties for reducing the computational complexity.

21. A method according to claim 1, wherein said shape constraints are convex piece-wise linear bounding functions, and said determining of dimensions, and position of said elements is performed using linear programming with a linear objective function of slice dimensions.

22. A method according to claim 1, wherein said shape constraints are monotonously non-increasing piece-wise linear bounding functions, and said calculation of dimensions, position, and orientation is performed by minimizing at least one of area, perimeter, and any other quasi-concave objective function of the dimensions of the enveloping rectangle, which is monotone in both its arguments.

23. A method according to claim 1, wherein said surface is a mask for circuit integration.

24. A method according to claim 1, comprising the further steps of:

selecting a pin distribution over the sides of at least a portion of said elements; and

determining said orientation of said elements using said pin distribution and said configuration of said element centers.