Structure of stacked, complementary MOS field effect transistor circuits

• US 4,555,721 A
• Filed: 11/04/1983
• Issued: 11/26/1985
• Est. Priority Date: 05/19/1981
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bertin, Claude L., Bansal, Jai P., Troutman, Ronald R.
• Primary Examiner(s): Edlow, Martin H.
• Assistant Examiner(s): JACKSON JR, JEROME
• Application Number:
  US06/548,733
• Time in Patent Office: 753 Days
• Field of Search: 357/42, 357/59
• US Class Current: 257/69
• CPC Class Codes: H01L 21/268 using electromagnetic radiation, e.g. laser radiation
• CPC Class Codes: H01L 21/8238 Complementary field-effect transistors, e.g. CMOS
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30

Abstract

A method is disclosed for fabricating series and/or parallel connected P channel and N channel FET device topologically connected in a CMOS configuration, where the individual FET devices share a common gate sandwiched between them, forming a five terminal device. A new device structure and complementary MOSFET circuitry is also disclosed. The disclosed process produces devices and circuits which overcome the main disadvantage of prior art CMOS transistors, namely excessive area consumption and parasitic effects.

Claims

1. A stacked CMOS, two-input NAND integrated circuit comprising:

a first diffusion bar of N-type conductivity in a P-type silicon substrate;

a second diffusion bar of N-type conductivity in said substrate located in spaced, parallel relationship with said first bar forming a first N channel region therebetween;

a third diffusion bar of N-type conductivity in said substrate located in spaced, parallel relationship with said second bar forming a second N channel region therebetween;

a first logical input gate electrode juxtaposed over said first N channel region which is covered by an insulating layer, with said first N channel region forming a first N channel FET device;

a first layer of phosphosilicate glass on top of said first gate electrode;

a second logical input gate electrode juxtaposed over said second N channel region which is covered by an insulating layer, with said second N channel region forming a second N channel FET device;

a second layer of phosphosilicate glass on top of said second gate electrode;

a layer of laser annealed silicon having a first N-type portion covering said juxtaposed portion of said first gate electrode and formed by the diffusion of phosphorous atoms out from said first layer of phosphosilicate glass, a first P-type portion juxtaposed over said first bar and a second P-type portion juxtaposed over said second bar, forming a first P channel FET device;

said silicon layer having a second N-type portion covering said juxtaposed portion of said second gate electrode and formed by the diffusion of phosphorous atoms out from said second layer of phosphosilicate glass, and a third P-type portion juxtaposed over said third bar forming a second P channel FET device with said second P-type portion;

said first diffusion bar connected to a logical output terminal, said third diffusion bar connected to ground potential, said second diffusion bar operating as the source of said first N channel FET and the drain of said second N channel FET and said third diffusion bar operating as the source of said second N channel FET;

said first and third P-type portions of said layer connected to said logical output, said second P-type portion connected to a positive potential to operate as the source for both said first and second P channel devices, and said third P-type portion operating as the drain for said second P channel device.

2. A stacked CMOS, two-input NOR integrated circuit, comprising:

a first diffusion bar of N-type conductivity in a P-type silicon substrate;

a second diffusion bar of N-type conductivity in said substrate located in spaced, parallel relationship with said first bar forming a first N channel region therebetween;

a third diffusion bar of N-type conductivity in said substrate located in spaced, parallel relationship with said second bar forming a second N channel region therebetween;

a first logical input gate electrode juxtaposed over said first N channel region which is covered by an insulating layer, with said first N channel region forming a first N channel FET device;

a first layer of phosphosilicate glass on top of said first gate electrode;

a second logical input gate electrode juxtaposed over said second N channel region which is covered by an insulating layer, with said second N channel region forming a second N channel FET device;

a second layer of phosphosilicate glass on top of said second gate electrode;

a layer of laser annealed silicon having a first N-type portion covering said juxtaposed portion of said first gate electrode and formed by the diffusion of phosphorous atoms out from said first layer of phosphosilicate glass, a first P-type portion juxtaposed over said first bar and a second P-type portion juxtaposed over said second bar, forming a first P channel FET device;

said silicon layer having a second N-type portion covering said juxtaposed portion of said second gate electrode and formed by the diffusion of phosphorous atoms out from said second layer of phosphosilicate glass, and a third P-type portion juxtaposed over said third bar forming a second P channel FET device with said second P-type portion;

said diffusion bar connected to a logical output terminal, said second diffusion bar connected to said ground potential, operating as the source of said first N channel FET and the source of said second N channel FET and said third diffusion bar connected to said output terminal operating as the drain of said second N channel FET;

said third P-type portion of said layer connected to said logical output, said first P-type portion connected to a positive potential to operate as the source for said first P channel device, said second P-type portion operating as the drain for said first P channel device and as the source for said second P channel device.

3. A stacked CMOS, flip-flop integrated circuit, comprising:

a first diffusion bar of N-type conductivity in a P-type silicon substrate;

a second diffusion bar of N-type conductivity in said substrate located in spaced, parallel relationship with said first bar forming a first N channel region therebetween;

a third diffusion bar of N-type conductivity in said substrate located in spaced, parallel relationship with said second bar forming a second N channel region therebetween;

a first logical input gate electrode juxtaposed over said first N channel region which is covered by an insulating layer, with said first N channel region forming a first N channel FET device;

a first layer of phosphosilicate glass on top of said first gate electrode;

a second logical input gate electrode juxtaposed over said second N channel region which is covered by an insulating layer, with said second N channel region forming a second N channel FET device;

a second layer of phosphosilicate glass on top of said second gate electrode;

a layer of laser annealed silicon having a first N-type portion covering said juxtaposed portion of said first gate electrode and formed by the diffusion of phosphorous atoms out from said first layer of phosphosilicate glass, a first P-type portion juxtaposed over said first bar and a second P-type portion juxtaposed over said second bar, forming a first P channel FET device;

said silicon layer having a second N-type portion covering said juxtaposed portion of said second gate electrode and formed by the diffusion of phosphorous atoms out from said second layer of phosphosilicate glass, and a third P-type portion juxtaposed over said third bar forming a second P channel FET device with said second P-type portion;

said first diffusion bar connected to a first logical output terminal, said second difffusion bar connected to ground potential, said third diffusion bar connected to a second logical output terminal, said second diffusion bar operating as the source of said first N channel FET and the source of said second N channel FET;

said second P-type portion connected to a positive potential to operate as the source for both said first and second P channel devices, said first diffusion bar connected to said first P-type portion and said third diffusion bar connected to said third P-type portion;

said first gate electrode connected to said third P-type portion and said second gate electrode connected to said first P-type portion.