Power line carrier FSK data system

• US 4,556,866 A
• Filed: 03/16/1983
• Issued: 12/03/1985
• Est. Priority Date: 03/16/1983
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Honeywell Incorporated (Honeywell International Inc.)
• Inventors: Gorecki, James L.
• Primary Examiner(s): Ng, Jin F.
• Assistant Examiner(s): Kuntz, Curtis
• Application Number:
  US06/475,802
• Time in Patent Office: 993 Days
• Field of Search: 375/45, 375/62, 375/65, 375/81, 375/88, 375/120, 375/9, 340/310 A, 340/310 R, 329/50
• US Class Current: 375/272
• CPC Class Codes: H04B 2203/5408 using protocols
• CPC Class Codes: H04B 2203/5416 by adding signals to the wave form of the power source
• CPC Class Codes: H04B 2203/542 using zero crossing information
• CPC Class Codes: H04B 2203/5491 using filtering and bypassing
• CPC Class Codes: H04B 3/542 the information being in digital form
• CPC Class Codes: H04L 27/10 Frequency-modulated carrier systems, i.e. using frequency-shift keying H04L27/32 takes precedence

Abstract

A frequency shift keyed (FSK) data transmission system utilizes existing power lines to transmit data by superimposing a high frequency FSK signal on the power line carrier. A transmitter includes a phase locked loop which is locked on the power line carrier frequency and which synthesizes the FSK signal and a timing signal which defines the data rate of the transmitter. As each bit is transmitted, an oscillator control signal either speeds up or slows down the loop oscillator temporarily to produce the FSK signal. A receiver demodulates the data transmission from the power line by separating a power line carrier frequency component and a FSK signal component. The receiver includes a phase locked loop which locks onto the power line carrier frequency and which synthesizes a reference frequency and a timing signal which defines the data rate of the receiver. The receiver also includes a frequency discriminator circuit which compares the FSK signal with the synthesized reference signal and produces a digital data output signal at the data rate synthesized by the phase locked loop.

Claims

1. A data communication system for communicating data between a first and a second location over an electrical power line which also carries alternating current electrical power having a frequency f_PC, the system comprising:

transmitter means at the first location for providing to the power line a periodic frequency shift keyed (FSK) signal representing a serial input stream of binary bits, the FSK signal having a frequency f_FSK and a predetermined data rate, wherein f_FSK is greater than the data rate, and the date rate is greater than f_PC, the transmitter means comprising;

first means for deriving from the power line a signal having frequency f_PC ;

first phase locked loop means locked to the signal having frequency f_PC for synthesizing the FSK signal and a transmitter timing signal which determines the data rate, wherein the first phase locked loop means comprises;

first oscillator means for producing the FSK signal with a frequency f_FSK which is a function of a first control signal and a second control signal;

divider means for dividing the FSK signal to produce a synthesized signal having a frequency f_SPC which is equal to f_PC when the first phase locked loop means is in lock and to produce the transmitter timing signal which defines a bit time period for each bit of the serial input stream;

first phase detector means for providing a first phase detector output which is a function of a phase comparison of the signal having frequency f_PC and the synthesized signal having frequency f_SPC ; and

means for providing the first control signal as a function of the first phase detector output;

control means for providing the second control signal during each bit time period which causes the first oscillator means to produce the FSK signal with a frequency f_FSK which is greater than a reference frequency f_O to represent a bit of the input stream having first binary state and is less than f_O to represent a bit of the input stream having a second binary state;

means for superimposing the FSK signal onto the power line; and

receiver means at the second location for providing a periodic serial output stream of binary bits, the receiver means comprising;

second means for deriving from the power line a signal having frequency f_PC ;

second phase locked loop means locked to the signal having frequency f_PC for synthesizing a reference signal having frequency f_O and a receiver timing signal which determines the data rate, wherein the second phase locked loop means comprises;

second oscillator means for producing the reference signal with a frequency f_O which is a function of a control signal;

divider means for dividing the reference signal to produce a synthesized signal having a frequency f_SPC which is equal to f_PC when the second phase locked loop means is in lock and to produce a receiver timing signal which defines a bit time period for each bit of the serial output stream;

second phase detector means for providing a second phase detector output which is a function of a phase comparison of the signal having frequency f_PC and the signal having frequency f_SPC ; and

means for providing the control signal to the second oscillator means as a function of the second phase detector output;

means for deriving the FSK signal from the power line; and

frequency discriminator means responsive to the receiver timing signal for providing the periodic serial output stream of binary bits as a function of periodic comparison of the FSK signal and the reference signal.

2. The system of claim 1 wherein the frequency discriminator means makes the frequency comparison of the FSK signal and the reference signal during each bit time period defined by the receiver timing signal from the second phase locked loop means.

3. The system of claim 1 wherein the first means and the second means each comprises:

low pass filter means connected to the power line for producing a filtered alternating current signal having frequency f_PC ; and

zero crossing detector means for producing the signal of frequency f_PC based upon selected zero crossings of the filtered alternating current signal.

4. A transmitter of a periodic frequency shift keyed (FSK) signal carried on an electrical power line which also carries alternating current electrical power having a frequency f_PC, the FSK signal having a frequency f_FSK during each of a sequence of bit time periods which represent binary bits to be transmitted, the transmitter comprising:

means for deriving from the power line an input signal having frequency f_PC ;

phase locked loop means locked to the input signal having frequency f_PC for synthesizing the FSK signal and a transmitter timing signal which determines the bit time periods, wherein the phase locked loop means comprises;

oscillator means for producing the FSK signal with a frequency f_FSK which is a function of a first control signal and a second control signal;

divider means for dividing the FSK signal to produce a synthesized signal having a frequency f_SPC which is equal to f_PC when the first phase locked loop means is in lock and to produce the transmitter timing signal which defines the bit time period for each bit to be transmitted;

phase detector means for providing a first phase detector output which is a function of a phase comparison of the signal having frequency f_PC and the synthesized signal having frequency f_SPC ; and

means for providing the first control signal as a function of the first phase detector output;

control means for providing the second control signal during each bit time period which causes the oscillator means to produce the FSK signal with a frequency f_FSK which is greater than a reference frequency f_O if the bit to be transmitted has a first binary state and which is less than f_O if the bit to be transmitted has a second binary state; and

means for providing the FSK signal to the power line.

5. The system of claim 4 wherein the means for deriving comprises:

low pass filter means connected to the power line for producing a filtered alternating current signal having frequency f_PC ; and

zero crossing detector means for producing the input signal based upon selected zero crossings of the filtered alternating current signal.

6. A receiver for demodulating a periodic frequency shift keyed (FSK) signal carried on an electrical power line which also carries alternating current electrical power having a frequency f_PC to produce a periodic binary output signal, at a predetermined data rate, which has a first state when the FSK signal has a frequency f_FSK which is greater than a reference frequency f_O and which has a second state when f_FSK is less than f_O, wherein frequencies f_O and f_FSK are greater than the data rate and wherein the data rate is greater than f_PC, the receiver comprising:

means for deriving from the power line a first input signal having the frequency f_PC ;

means for deriving from the power line a second input signal having the frequency f_FSK ;

phase locked loop means for locking onto frequency f_PC of the first input signal and producing a first synthesized signal having the frequency f_O and a second synthesized signal having a frequency which is related to the predetermined data rate;

the phase locked loop comprising;

oscillator means for producing the first synthesized signal having frequency f_O which is a function of an oscillator control signal;

divider means for dividing the frequency of the first synthesized signal to produce the second synthesized signal and a third synthesized signal of frequency f_SPC which is equal to f_PC when the phase locked loop is in lock;

loop phase detector means for providing a phase detector output which is a function of a phase comparison of the first input signal and the third synthesized signal; and

means for providing the oscillator control signal as a function of the phase detector output to cause the third synthesized signal to have frequency f_SPC =f_PC and be locked in phase with the first input signal; and

frequency discriminator means for providing the binary output signal, at the data rate determined by the second synthesized signal, as a function of a comparison of the second input signal and the first synthesized signal.

7. The receiver of claim 6 wherein the means for deriving the first input signal comprises:

low pass filter means connected to the power line producing a filtered alternating current signal having frequency f_PC ; and

zero crossing detector means for producing the first input signal based upon selected zero crossings of the filtered alternating current signal.

8. The receiver of claim 7 wherein the zero crossing detector means produces a first input signal which exhibits a signal transition in response to selected zero crossings of the filtered alternating current signal.

9. The receiver of claim 8 wherein the selected zero crossings are upward zero crossings.

10. The receiver of claim 6 wherein the frequency discriminator means provides the binary output signal as a function of a phase comparison of the second output signal and the first synthesized signal.

11. The receiver of claim 10 wherein the frequency discriminator means comprises:

discriminator phase detector means for providing a phase detector output as a function of the second input signal and the first synthesized signal;

integrator means for integrating the phase detector output to produce an integrator signal;

output means for providing the binary output signal as a function of the integrator signal; and

means responsive to the second synthesized signal for periodically resetting the integrator means to an initial state.

12. The receiver of claim 11 wherein the output means comprises:

comparator means for comparing the integrator signal with a reference level to produce a comparator output signal; and

data latch means responsive to the second synthesized signal for periodically producing the binary output signal as a function of the comparator output signal.

13. The receiver of claim 12 wherein the second synthesized signal defines a sequence of bit time periods, and wherein the data latch means produces the digital output signal during each bit time as a function of the comparator output signal at the end of a preceding bit time.

14. The receiver of claim 13 wherein the means for periodically resetting clears the integrator means at the beginning of each bit time period.

15. The receiver of claim 11 wherein the discriminator phase detector means is a tristate phase detector.

16. The receiver of claim 6 wherein the second synthesized signal defines a sequence of bit time periods, and wherein the frequency discriminator means provides the binary output signal during each bit time period as a function of a comparison of the second input signal and the first synthesized signal during a preceding bit time.

17. The receiver of claim 6 wherein the means for deriving a first input signal comprises a low pass filter, and wherein the means for deriving a second input signal comprises a band pass filter.