Single crystal dual microprocessor computing system
First Claim
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1. A single crystal dual microprocessor computing system comprising:
- a plurality of signal generating devices, each device generating an electrical signal having an informational value;
a plurality of output devices each actuable by one or more control signals;
dual microprocessors electrically connected in parallel, each receiving at least a portion of the electrical signals from said generating devices and operable for calculating control signals for actuating one or more output devices according to control laws stored in said microprocessors and information supplied from said electrical signals;
said microprocessors each having a first and second clock input terminals; and
a single crystal element having an output lead and a return lead, said output lead electrically connected to said first clock input terminals of said dual microprocessors, said return lead electrically connected to said second clock input terminal of said first of said dual microprocessors, and said second clock input of said second of said dual microprocessors connected to electrical ground, whereby said first microprocessor operates as a master microprocessor for synchronizing said second microprocessor to said first microprocessor.
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Abstract
A single crystal (100) dual microprocessor (26, 28) computing system utilizes a single frequency determining element (100) connected across the input pins of one of the microprocessors (26) and the output (102) of the element is connected to one input pin of the second microprocessor (28). The second pin of the second microprocessor (28) is connected to electrical ground (106). This configuration reduces the effective output impedance and results in higher oscillator amplitudes.
26 Citations
1 Claim
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1. A single crystal dual microprocessor computing system comprising:
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a plurality of signal generating devices, each device generating an electrical signal having an informational value; a plurality of output devices each actuable by one or more control signals; dual microprocessors electrically connected in parallel, each receiving at least a portion of the electrical signals from said generating devices and operable for calculating control signals for actuating one or more output devices according to control laws stored in said microprocessors and information supplied from said electrical signals; said microprocessors each having a first and second clock input terminals; and a single crystal element having an output lead and a return lead, said output lead electrically connected to said first clock input terminals of said dual microprocessors, said return lead electrically connected to said second clock input terminal of said first of said dual microprocessors, and said second clock input of said second of said dual microprocessors connected to electrical ground, whereby said first microprocessor operates as a master microprocessor for synchronizing said second microprocessor to said first microprocessor.
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Specification
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Current AssigneeSiemens-Bendix Automotive Electronics LP
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Original AssigneeAllied Corp. (Honeywell International Inc.)
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InventorsWeber, Robert E., Wright, Danny O.
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Primary Examiner(s)Ruggiero, Joseph
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Assistant Examiner(s)Grossman, Jon D.
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Application NumberUS06/499,114Time in Patent Office921 DaysField of Search364/131, 364/132, 364/133, 364/200, 364/431.06, 364/431.07, 364/723, 364/900, 340/825.06US Class Current700/4CPC Class CodesF02D 41/266 the computer being backed-u...G06F 1/10 Distribution of clock signa...
