Semiconductor memory with delay means to reduce peak currents

• US 4,556,961 A
• Filed: 05/19/1982
• Issued: 12/03/1985
• Est. Priority Date: 05/26/1981
• Status: Expired due to Term

• Current Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
• Original Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
• Inventors: Asano, Masamichi, Iwahashi, Hiroshi
• Primary Examiner(s): Hecker, Stuart N.
• Assistant Examiner(s): Gossage, Glenn A.
• Application Number:
  US06/379,852
• Time in Patent Office: 1,294 Days
• Field of Search: 365/189, 365/194, 365/203, 365/205, 365/206, 365/208, 365/227, 365/207
• US Class Current: 365/194
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 8/14 Word line organisation; Word line lay-out

Abstract

A semiconductor device comprises a plurality of data supply circuits, output circuits for producing a plurality of data delivered from the data supply circuit and delay circuit for transferring respective data from each data supply circuit to a different output circuit with a different delay time. Each data supply circuit includes a plurality of row lines, a row decoder for selecting the row line in response to an address signal, a plurality of memory cell arrays including memory cells selectively driven by the row line and storing data, a plurality of column lines to receive data read out from the memory cell array, and a column decoder for selecting said column lines. The delay circuit prevents a plurality of data from being simultaneously outputted.

Claims

1. A semiconductor device comprising:

data supply means;

a plurality of output means, each connected to said data supply means;

means for causing all of said output means to change simultaneously from operation states to non-operation states, said simultaneous change causing means including a first control line through which a first control signal is transferred; and

delay means, connected to said plurality of output means, for causing said plurality of output means to operate and output data from said data supply means at different times in order to reduce peak instantaneous currents, said delay means including at least one depletion type MOS transistor whose conduction path is in series with a second control line through which a second control signal of said output means is transferred, the gate of said MOS transistor being connected to the end of said second control line to which said second control signal enters, and said second control signal changing levels in synchronism with said first control signal.

2. A semiconductor device comprising:

data supply means having

a plurality of row lines,

a row decoder for selecting one of said row lines in response to an address signal,

a plurality of memory cell arrays each including nemory cells for storing data, said memory cells being arranged in rows and columns and being driven by said selected row line,

a plurality of column lines to receive data read out from said driven memory cells, and

a column decoder for selecting one of said plurality of column lines for delivering from said data supply means the data received from said cells;

output means for producing a plurality of data delivered from said data supply means;

precharge means for precharging said column lines; and

precharge time setting means for setting precharge times for said precharge means to correspond to the distances on a row line from said row decoder, said precharge time setting means further including

an address buffer circuit for producing a plurality of successive signals in response to said address signal,

an address change detecting circuit for producing a precharge set signal to form a precharge signal by detecting a change of said address signal, said address change detecting circuit being supplied with certain of said plurality of signals from said address buffer circuit,

a delayed chip enable signal generating circuit for producing a delayed chip enable signal delayed a given amount of time in response to a chip enable signal inputted to said semiconductor device,

an address buffer output delay circuit having as inputs an address buffer output signal and an inverted address buffer output signal received from said address buffer circuit, said address buffer output delay circuit producing a delayed address buffer output signal and a delayed inverted address buffer output signal both delayed a preset time from said address buffer output signal and said inverted address buffer output signal, respectively, when said chip enable signal is "one", said address buffer output signal and said inverted address buffer output signal both being connected to two output terminals,

a gate circuit connected between said two output terminals and being controlled by a signal from said delayed chip enabled signal generating circuit,

a dummy row decoder for receiving signals from said two output terminals,

a dummy row line driven by an output signal from said dummy row decoder, and

an end timing circuit for causing the end of said precharging in response to the detection of a potential at a given point on said dummy row line.