Semiconductor device and process for manufacturing the same

• US 4,557,036 A
• Filed: 03/25/1983
• Issued: 12/10/1985
• Est. Priority Date: 03/31/1982
• Status: Expired due to Fees

• Current Assignee: Nippon Telegraph and Telephone Corporation
• Original Assignee: Nippon Telegraph and Telephone Corporation
• Inventors: Oikawa, Hideo, Kyuragi, Hakaru
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): Hey, David A.
• Application Number:
  US06/479,135
• Time in Patent Office: 991 Days
• Field of Search: 29/571, 29/578, 29/591, 29/576 B, 148/1.5, 148/DIG. 20, 148/DIG. 105, 148/DIG. 103, 148/DIG. 117, 357/67, 357/33, 357/23, 357/65, 427/93, 427/88, 427/95
• US Class Current: 438/592
• CPC Class Codes: H01L 21/28512 on semiconductor bodies comprising elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 21/76825 by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc. plasma treatment H01L21/76826
• CPC Class Codes: H01L 21/76828 thermal treatment
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10S 148/103 Mask, dual function, e.g. diffusion and oxidation
• CPC Class Codes: Y10S 148/105 Masks, metal

Abstract

A multilayer structure comprising a Si layer/ a refractory metal oxide layer/ a refractory metal layer/ is subjected to annealing in an atmosphere of hydrogen or an inert gas mixed with hydrogen, thereby converting the multilayer structure into a multilayer structure comprising a Si layer/an inner SiO₂ layer formed by internal oxidation of Si/a refractory metal layer. The inner SiO₂ layer is selectively formed only on the surface of the refractory metal layer, since Si is internally oxidized from the side of the refractory metal layer. In case of gate electrode of a MISFET, the gate electrode and a contact hole for source or drain electrode are positioned in self-alignment with each other via the inner SiO₂ layer. The distance between the gate electrode and the source or drain electrode is determined by the thickness of the inner SiO₂ layer. A semiconductor device with a high density and a high speed is realized.

Claims

1. A process for manufacturing a semiconductor device, comprising the steps of:

(1) applying a refractory metal layer onto a base;

(2) forming a refractory metal oxide layer on the surface of said refractory metal layer;

(3) forming a silicon layer on said refractory metal oxide layer; and

(4) annealing the resulting structure in an atmosphere containing hydrogen to form an internally oxidized silicon layer substantially at the interfaces of said refractory metal layer and said silicon layer.

2. A process as claimed in claim 1, wherein said step (2) comprises at least the sub-steps of:

(2-1) oxidizing the surface portion of said refractory metal layer in a low temperature atmosphere containing oxygen; and

(2-2) annealing the resulting product in an inert gas atmosphere at a high temperature so as to form said refractory metal oxide layer.

3. A process as claimed in claim 1, wherein said step (2) comprises the sub-step of oxidizing the surface portion of said refractory metal layer in an atmosphere of an inert gas mixed with oxygen.

4. A process as claimed in claim 1, which further comprises the step of forming a silicon dioxide layer on the surface of said silicon layer between said steps (3) and (4).

5. A process as claimed in claim 1, wherein said base comprises a substrate and an insulating layer thereon, and said refractory metal layer has a predetermined pattern formed on said substrate via said insulating layer interposed therebetween, which further comprises the step of forming at least one contact hole in said insulating layer in self-alignment with at least one edge of the shaped refractory metal layer via said refractory metal oxide layer interposed therebetween, between said steps (2) and (3), and wherein said silicon layer in said step (3) is so formed as to cover said at least one contact hole and said refractory metal layer.

6. A process as claimed in claim 5, which further comprises the step of forming a silicon dioxide layer on the surface of said layer of silicon between said steps (3) and (4).

7. A process as claimed in claim 1, wherein said base comprises a substrate and an insulating layer thereon, and said refractory metal layer has a predetermined shape formed on said substrate via said insulating layer interposed therebetween, which further comprises the step of forming at least one contact hole in said insulating layer in self-alignment with at least one edge of the shaped refractory metal layer via said refractory metal layer interposed therebetween, between said steps of (1) and (2), and wherein said silicon layer in said step (3) is so formed as to cover said at least one contact hole and said refractory metal layer.

8. A process as claimed in claim 7, which further comprises the step of forming a silicon dioxide layer on the surface of said silicon layer between said steps (3) and (4).