Programmable digital cardiac pacer

• US 4,557,266 A
• Filed: 09/29/1982
• Issued: 12/10/1985
• Est. Priority Date: 12/13/1979
• Status: Expired due to Term

• Current Assignee: Edwards Lifesciences Corporation
• Original Assignee: American Hospital Supply Corp. (Baxter International Inc.)
• Inventors: Schober, Robert C.
• Primary Examiner(s): Kamm, William E.
• Application Number:
  US06/427,782
• Time in Patent Office: 1,168 Days
• Field of Search: 128/419 PG, 128/696, 128/702-706, 128/708
• US Class Current: 607/30
• CPC Class Codes: A61B 5/316 Modalities, i.e. specific diagnostic methods
• CPC Class Codes: A61B 5/346 Analysis of electrocardiograms
• CPC Class Codes: A61B 5/7203 for noise prevention, reduction or removal
• CPC Class Codes: A61N 1/3622 comprising two or more electrodes co-operating with different heart regions

Abstract

A cardiac pacer has separate digital filter circuits for sensing atrial and ventricular activity. Parameter data stored in memory is used by the digital filters for identifying the various components of cardiac activity, such as the P, R and T waves, as well as for identifying Premature Ventricular Contractions (PVC). A Ventricular Rate Time Out period is established from the last natural beat or stimulating pulse; and if a P wave or natural R wave is not sensed during that period, the system generates a stimulating pulse and, using T wave parameters in the ventricular filter, tests to verify capture.

Claims

1. Implantable cardiac pacing apparatus comprising:

electrode means including at least a first electrode adapted to stimulate the heart;

signal detector means including sensing means responsive to a cardiac signal on said electrode means;

digital filter means receiving the signal sensed by said sensing means for quantizing said sensed signal and continuously generating digital words representative of the slope of said sensed signal over a sample time window;

parameter memory means for storing signals representative of predetermined selection criteria data for defining at least one component of a cardiac cycle signal;

selection circuit means;

controller circuit means for extending said signals to said selection circuit means, said selection circuit means comparing the quantized output signals of said filter means with said selection criteria signals for generating a detection signal if said digital slope words meet said predetermined selection criteria; and

generator means for generating a stimulating signal and coupling the same to said electrode means if said selection circuit means fails to generate said detection signal within a predetermined time from a previous detection signal or a previous stimulating signal.

2. The apparatus of claim 1 further comprising timing means for generating timing signals synchronized with a predetermined portion of a cardiac cycle, said generator means being responsive to said timing signals for generating said stimulating signa.

3. The apparatus of claim 2 wherein said timing means generates a refractory signal representative of ventricular refractory period in a cardiac cycle, said selection circuit means being responsive to said refractory signal and said selection criteria signals representative of a T wave for generating a capture verification detection signal during a refractory period following a stimulating signal if a T wave is detected in such refractory period.

4. The apparatus of claim 3 further comprising means responsive to said selection circuit means for increasing the energy of a subsequent stimulating signal if said selection circuit means does not detect a T wave during said refractory period.

5. The apparatus of claim 4 wherein said timing means further generates a rate time out signal in each cardiac cycle subsequent to said refractory period and wherein said apparatus further comprises parameter signal storage means for storing a plurality of data words representative of different selection criteria;

said controller circuit means responsive to said timing means for coupling one selection criteria data word to said selection circuit means during said refractory period for identifying a T wave and for coupling a second selection criteria data word to said selection circuit means during said rate time out period for identifying an R wave in said cardiac signal.

6. The apparatus of claim 5 further comprising second filter means receiving the signal sensed by said sensing means for quantizing said sensed signal and continuously generating digital words representative of the slope of said sensed signal over a sample time window;

and second selection circuit means responsive to the quantized output signals of said second filter means for detecting an atrial contraction signal during said rate time out period, said controller means being responsive to said second selection circuit means for establishing a predetermined P-R time out period in response to the detection of an atrial contraction signal in said rate time out period irrespective of the time remaining in said rate time out period prior to said detection of said atrial contraction signal, whereby the heart is permitted to synchronize contraction of the ventricle with a sensed contraction of the atrium for said P-R time and said first selection circuit means is set to detect an R wave during said P-R time, said generator means generating said stimulating signal if said R wave is not detected in said P-R time period.

7. The apparatus of claim 5 wherein said controller circuit means is responsive to the detection of an R wave representing a natural heartbeat during the rate time out period for coupling selection criteria signals during the succeeding refractory time period to said filter means, said selection criteria signals being representative of a predetermined noise level of detection said controller being responsive to a first signal detection during said refractory time comprising a second part of refractory for coupling selection criteria signals to said filter means during said second part of refractory period for detecting a PVC signal therein said system further including reversion counter means and means for incrementing said reversion counter means and for each PVC couplet detected and for reverting to fixed rate pacing if a predetermined count of said couplet is reached.

8. The apparatus of claim 7 wherein said controller circuit means couples one set of selection criteria signals to said selection circuit means during a first part of said refractory time period prior to said first signal detection during said refractory period, and a second set of selection criteria signals for the second part of said refractory period.

9. The apparatus of claim 8 wherein said controller circuit means couples selection criteria signals to said selection circuit means for detecting a T wave, an R wave, or a PVC during the first part of a refractory period if said system had detected a natural heartbeat in the previous cardiac cycle and for detecting an R wave or a PVC in the second part of such refractory period.

10. The apparatus of claim 7 wherein said controller circuit means in response to the generation of a stimulating signal by said generator means couples selection criteria signals from said memory means to said selection circuit means during said refractory time period for detecting a T wave, said controller circuit means in response to the detection of a T wave in said refractory period entering a second part of said refractory period couples selection criteria signals to said selection circuit means for detecting a signal of greater magnitude than the T wave during said second part of refractory.

11. The apparatus of claim 9 further including reversion counter circuit means and PVC counter circuit means wherein said controller circuit means couples selection criteria signals to said selection circuit means during said second part of refractory representative of either an R wave or a PVC, said controller circuit means being responsive to the detection of a PVC during said second part of refractory for incrementing said reversion counter circuit means and said PVC counter circuit means, said system being responsive to a predetermined reversion count for reverting to fixed rate pacing when said predetermined count is reached.

12. The apparatus of claim 10 wherein said controller circuit means is responsive to the detection of an R wave in said second part of refractory for incrementing said reversion counter circuit means.

13. The apparatus of claim 10 wherein said timing circuit means further penetrates a PVC period signal following said refractory period, said controller circuit means coupling selection criteria signals to said selection circuit means for detecting a PVC signal during said PVC period, said apparatus resetting the cardiac cycle time for detecting a further PVC signal during a refractory period, said apparatus continuing to increment said reversion counter circuit means for each detection of a PVC either in said refractory time period or said PVC time period and for existing said PVC time period only if a PVC signal is not detected in said PVC time period.

14. The apparatus of claim 1 further comprising timing means for generating timing signals defining a commencement of a cardiac cycle and representing respectively a refractory time period said a rate time out period, each of predetermined duration;

and controller circuit means for coupling first selection criteria signals from said memory means to said selection circuit means during said refractory time period and for coupling second selection criteria signals from said memory means to said selection circuit means during said rate time out period.

15. The apparatus of claim 14 wherein said selection criteria signals define slope ranges of said cardiac signal.

16. The apparatus of claim 14 wherein said electrode means comprises a first sensing electrode associated with the atrium of the heart and a second electrode implanted in the ventricle of the heart for both sensing ventricular activity and for coupling said stimulating signal from said generating means to said ventricle, said signal detector means comprising first and second detector means associated respectively with said first and second electrodes and having separate selection criteria signals for detecting respectively a T wave identifying atrial contraction and an R wave identifying ventricular contraction.

17. The apparatus of claim 16 wherein said memory means for said second detector means includes first selection criteria signals representative of a T wave and second selection criteria signals representative of an R wave;

said system further comprising controller circuit means responsive to said timing signals for coupling said T wave selection criteria signals to said selection circuit means of said second signal detector means during a refractory time period whereby said second detector means is set to define a T wave for capture verification during said refractory time, said controller circuit means being further operative to couple said R wave selection criteria signals to said selection circuit means of said second signal detector means during said rate time out period whereby said second signal detector circuit means is set to identify an R wave during said rate time out period.

18. The apparatus of claim 17 wherein said timing means further generates a PVC time period signal between said refractory time period signal and said rate time out period signal, said memory means further storing selection criteria signals representative of a PVC cardiac signal, said controller means coupling said PVC selection criteria signals to said selection circuit means during said PVC time period in response to the generation of said PVC time period signal.

19. The apparatus of claim 18 further comprising PVC counter circuit means, means for incrementing said PVC counter circuit means for each detection of a premature ventricular contraction during said PVC time period, said timing means generating a rate limit refractory time period signal in response to the detection of a premature ventricular contraction, said detector means being set to detect a PVC signal during said rate limit time refractory period and for incrementing said PVC counter circuit means in response thereto, said system reverting to fixed rate pacing if said counter circuit means exceeds a predetermined count.

20. The apparatus of claim 18 further comprising tachycardia detection means responsive to a first detection of a premature ventricular contraction by said detection circuit means for timing the interval of such contractions;

and circuit means for generating stimulating output signals from said generator means at a rate higher than the normal cardiac cycle for a predetermined number of pulses in an attempt to eliminate a tachycardia condition sensed by said tachycardia direction means.

47. The apparatus of claim 19 wherein said first timing circuit means includes a crystal oscillator for generating said timing signals, said second timing circuit means comprising a voltage-controlled oscillator generating said rate limit enable signal having a period depending upon the terminal voltage of said battery.

21. Implantable cardiac pacing apparatus comprising:

electrode means including at least a first electrode adapted to stimulate the heart;

signal detector means including sensing means responsive to a cardiac signal on said electrode means; and

digital filter circuit means receiving the signal sensed by said sensing means for quantizing said sensed signal and being programmable for identifying predetermined selection parameters of said signal;

memory means for storing signals representative of predetermined selection criteria defined by said selection parameters for said signal including at least a first data word for identifying an R wave and a second data for identifying a T wave;

selection circuit means responsive to the quantized output signals of said digital filter means and said stored selection parameter signals for generating a detection signal if said quantized signals of said digital filter means meet said predetermined selection criteria;

timing circuit means for establishing timing signal representative of a cardiac cycle including a ventricular refractory period and a ventricular rate time out period; and

state controller circuit means responsive to said timing signals for coupling said T wave selection criteria data word from said memory means to said digital filter means during said refractory period and for coupling said R wave selection criteria data words from said memory means to said digital filter means during said ventricular rate time out period; and

pulse generator means for generating a stimulating pulse on said electrode means if said detector means fails to sense a natural heartbeat before the end of a ventricular rate time out period.

22. The apparatus of claim 21 further comprising:

event counter means for storing signals representative of the number of times said apparatus has generated a stimulating output signal and has not identified a T wave during the next succeeding ventricular refractory period.

23. The apparatus of claim 21 wherein said memory means stores a third data word representative of selection criteria for detecting a Premature Ventricular Contraction;

and further including

ventricular filter parameter control circuit means responsive to a programmed input word for coupling said T wave data word from said memory means to said digital filter means for detecting a T wave during a first part of the refractory period following the generation of a stimulating pulse.

24. The apparatus of claim 23 wherein said ventricular filter parameter control circuit means is responsive to the detection of a T wave during said first part of refractory for coupling one of said data words from said memory means to said digital filter means for detecting one of an R wave, T wave, or Premature Ventricular Contraction during a second part of refractory following said first part;

said apparatus further comprising reversion counter circuit means for counting detections in said second part of refractory; and

wherein said state controller circuit means is responsive to a predetermined count in said reversion counter circuit means for causing said pulse generator to generate stimulating pulses at a fixed rate in response to said timing circuit means.

25. The apparatus of claim 23 wherein said filter parameter control circuit means further includes circuit means responsive to the detection of a natural heartbeat in the ventricular rate time out period of a previous cardiac cycle for coupling one of said filter data words to said filter circuit means for setting said filter circuit means to detect a T wave, an R wave, or a PVC during said first part of refractory period and for thereafter setting said filter circuit means to detect a PVC during a second part of said refractory period;

said apparatus further comprising reversion counter circuit means for storing a cummulative count of detections during said second part of refractory period; and

circuit means responsive to a predetermined count in said reversion counter circuit means for forcing said apparatus into a fixed rate of pacing.

26. The apparatus of claim 25 wherein said last named circuit means forces said apparatus into a state of fixed rate pacing at the end of the next succeeding ventricular rate time out period.

27. The apparatus of claim 23 wherein said timing circuit means further generates a timing signal representative of a PVC time period following said ventricle refractory period and prior to said ventricular rate time out period;

said ventricular filter parameter control circuit means being responsive to said PVC timing signal for coupling said third data word to said digital filter circuit means for setting said filter circuit means for the detection of a PVC signal during said PVC time period;

said apparatus further including PVC counter circuit means for accumulating counts representative of PVC detections during said PVC time period; and

circuit means responsive to the detection of a PVC signal during said PVC time period for entering a PVC loop of operation in which said apparatus is prevented from entering said ventricular rate time out period and said parameter control circuit means resets said timing signal generator means, and sets said filter circuit means to detect a PVC signal during the next succeeding ventricle refractory and PVC time periods, and increments said PVC count during said detections, said filter parameter control circuit means being responsive to any such PVC detections during said succeeding refractory and PVC time periods for continuing operation in said PVC loop.

28. The apparatus of claim 27 further comprising automatic tachycardia override circuit means responsive to a predetermined count in said PVC counter circuit means for generating a train of stimulating pulses comprising a programmable predetermined number of such pulses.

29. The apparatus of claim 28 wherein said tachycardia override circuit means includes event counter means for storing a count representative of the number of times said tachycardia override circuit means is enabled and for thereafter enabling said apparatus to enter a different mode of operation.

30. Cardiac pacing apparatus comprising:

sensing means including an electrode adapted to sense a cardiac signal;

detector circuit means receiving said sensed cardiac signal for detecting a predetermined component of said signal and generating a signal defining the commencement of a cardiac cycle;

primary timing circuit means responsive to said commencement signal for generating a timing signal representative of the end of a ventricular rate time out period;

pulse generator means responsive to said timing signals for generating a stimulating pulse on said electrode means if said detector means has not detected a natural heartbeat with said ventricular rate time out period;

the improvement comprising;

first memory circuit means for storing a plurality of first data words, each defining a different duration for said ventricular rate time out period and storing a plurality of second data words, each defining a different time duration for said stimulating signal;

circuit means responsive to the application of a predetermined external signal for generating an internal signal in said pacing apparatus representative thereof;

status memory means storing a plurality of programmable status signals including a first programmable status signal having an enable and a disable state; and

temporary mode counter circuit means responsive to said internal signal and said timing signals for counting a predetermined number of cardiac cycles and including control circuit means responsive to said first status signals'"'"' being in an enable state for selecting one of said first data words from said memory means to define a predetermined cardiac rate and one of said second data words to define the width of stimulating pulse, said control circuit means of said temporary mode counter circuit means disabling operation of said apparatus at said programmed rate and pulse width after said counter temporary mode counter circuit means has counted a predetermined number of cardiac cycles.

31. The apparatus of claim 30 wherein said control circuit means is responsive to said first status signal'"'"'s being in an disabled state for permitting said apparatus to operate in a first magnet phase under program control for as long as an external magnet is applied generating said external signal.

32. The apparatus of claim 31 wherein said status memory means includes a second programmable status signal having an enabled and a disabled state;

said apparatus further comprising

state controller circuit means responsive to said second status signal'"'"'s being in said disabled state for disabling said detector circuit means, thereby causing said apparatus to operate in a fixed rate mode as long as an external magnet is applied.

33. The apparatus of claim 32 further comprising further control circuit means responsive to said apparatus being programmed either at a rate above a predetermined base rate or at a pulse width less than a predetermined safe duration for enabling said temporary mode counter circuit means to terminate operations under one or both of said conditions after a predetermined number of cardiac cycles.

34. The apparatus of claim 33 wherein said further control circuit means forces said apparatus to operate in an inherently safe mode after said predetermined number of cardiac cycles and secondary timing circuit means including secondary oscillator circuit means for determining parameters of the stimulating pulses.

35. The apparatus of claim 34 further comprising circuit means responsive to said second magnet phase signal for selectively disabling said detector circuit means and thereby causing said apparatus to operate in a fixed rate mode with a ventricular rate time out period determined by said secondary oscillator circuit means.

36. The apparatus of claim 34 further comprising:

secondary oscillator status memory means for storing first and second data words representative respectively of a high and a low cardiac pacing rate relative to a normal rate,

said temporary mode counter circuit means being responsive to said second magnet phase signal for communicating said second data word of said secondary oscillator status memory means to said timing circuit means to define the ventricular rate time out period, said apparatus being further responsive to internally stored signals representative of a desired amplitude and pulse width for said stimulating pulse for effecting the same in response to said second magnet phase signal.

37. The apparatus of claim 34 characterized in that said primary circuit means includes a crystal oscillator and said secondary timing circuit timing means includes a voltage controlled oscillator, and further including means responsive to the application of said external signal to said apparatus to cause said system to operate in said second magnet phase after said predetermined number of cardiac cycles counted by said temporary mode counter circuit means to thereby permit a physician to check out the back-up timing source, rate and pulse width irrespective of the condition of the primary timing source.

38. The apparatus of claim 37 wherein said apparatus includes means responsive to the removal of said magnet for generating a signal representative thereof;

and

said secondary oscillator circuit means generates a rate limit enable signal representative of a desired minimum ventricular rate time out period;

said primary timing circuit means defining the end of a ventricular rate time out period during normal operation; and

state controller circuit means responsive to a rate limit enable signal derived from said secondary oscillator means for disabling the generation of a stimulating pulse until said rate limit enable signal has occurred.

39. The apparatus of claim 38 wherein said apparatus is implanted in a patient, and further comprising:

rate limit means for storing signals representative of the number of sequential occurrences in which the ventricular rate time out period derived from said primary timing circuit means occurs prior to said rate limit enable signal derived from said secondary timing circuit means, such events being rate limit events;

said apparatus further comprising;

means responsive to the removal of said external signal for generating an internal signal representative thereof;

said temporary mode counter circuit means further inhibiting the counting of said rate limit events in said counter circuit means during a predetermined time following the generation of said signal representative of the removal of said external signal.

40. The apparatus of claim 30 wherein said status memory means further includes a second programmable status signal having an enable and a disable state;

tachycardia control circuit means responsive to said circuit means that is responsive to the application of a predetermined external signal, and to said second status signal'"'"'s being in an enable state, for selecting one of said first data words and one of said second data words from said first memory means when said external signal is applied for causing said pulse generator means to generate a predetermined number of pulses at a predetermined repetition rate and pulse width for interrupting a chain of tachycardia;

whereby a patient may generate said external signal if tachycardia is detected, and said apparatus will implement a tachycardia override mode under program control and exit said tachycardia override mode irrespective of further action by the patient.

41. The apparatus of claim 30 wherein said detector circuit means includes a delta modulator and said status memory means stores a second status signal having an enable state of an electrogram generation mode, said control circuit means being responsive to said internal signal representative of the application of said external signal for coupling the output of said delta modulator to an output signal transmitter implanted with said apparatus for transmitting externally the output signal of said delta modulator.

42. The apparatus of claim 41 wherein said control circuit means increments said temporary mode counter circuit means for each cardiac cycle during which the output of said delta modulator is connected to said output signal transmitter;

and wherein said control circuit means de-couples the output of the delta modulator to said signal transmitter after a predetermined number of cardiac cycles.

43. The apparatus of claim 42 wherein said detector circuit means comprises first detector circuit means for detecting ventricular cardiac activity and generating the signal representative thereof, and atrial detector circuit means for detecting atrial cardiac activity and for generating the signal representative thereof;

and said apparatus includes programmable means for selectively energizing one or both of said detector circuits.

44. The apparatus of claim 42 wherein said temporary mode counter circuit means is responsive to an internal signal representative of the removal of said external signal for continuing to couple said detector circuit means to said transmitter for a predetermined number of cardiac cycles folling the removal of said external signal;

whereby said system reverts to a normal mode of operation wherein cardiac cycle timing is defined by said timing circuit means under normal mode operation.

45. The apparatus of claim 42 wherein said timing means includes primary and secondary timing sources for generating ventricular rate time out signals, and further including control circuit means for inhibiting said pulse generator means until said rate time out signal of said secondary timing signal occurs, and for detecting the occurrence of said rate time out signal of said primary source before the occurrence of said rate time out signal of said secondary source to define a rate limit event;

each occurrence of said apparatus further comprising rate limit event counter circuit means for generating signals representative of the number of successive rate limit events;

said temporary mode counter circuit means inhibiting said rate limit counter circuit means from counting said rate limit events for a predetermined number of cycles following the generation of said electrogram under said normal operating mode conditions to thereby provide a recovery time for battery depletion.

46. Implantable cardiac pacing apparatus comprising:

electrode means including at least a first electrode adapted to stimulate the heart;

signal detector means connected to a battery for energization and including sensing means responsive to a cardiac signal on said electrode means;

filter means receiving the signal sensed by said sensing means for quantizing said sensed signal and continuously generating digital words representative of the slope of said sensed signal over a sample time window, parameter memory means for storing signals representative of predetermined selection criteria for defining at least one component of a cardiac cycle signal, selection circuit means responsive to the quantized output signals of said filter means and said stored selection criteria signals for generating a detection signal if said digitial slope words meet said predetermined selection criteria, timing means for generating timing signals defining a commencement of a cardiac cycle and representing respectively a refractory time period and a rate time out period, each of predetermined duration;

controller circuit means for coupling first selection criteria signals from said memory means to said selection circuit means during said refractory time period and for coupling second selection criteria signals from said memory means to said selection circuit means during said rate time out period, generator means for generating stimulating signal and coupling the same to said electrode means if said selection means fails to generate said detection signal within a predetermined time from a previous detection signal or a previous stimulating signal, and a second timing circuit means independent of said first timing circuit means for generating a rate limit enable signal from the battery a predetermined time after the commencement of a cardiac cycle and for inhibiting said pulse generator means until said rate limit enable signal has been generated.

48. Implantable cardiac pacing apparatus comprising:

electrode means including at least a first electrode adapted to stimulate the heart;

signal detector means including sensing means responsive to a cardiac signal on said electrode means; and

first digital filter circuit means receiving the signal sensed by said sensing means for quantizing said sensed signal and being programmable for identifying predetermined selection parameters of said signal;

memory means for storing signals representative of predetermined selection criteria defined by said selection parameters for said signal including at least a first data word for identifying an R wave and a second data word for identifying a T wave;

selection circuit means responsive to the quantized output signals of said first digital filter means and said stored selection parameter signals for generating a detection signal if said quantized signals of said first digital filter means meet said predetermined selection criteria;

timing circuit means for establishing timing signals representative of a cardiac cycle including a ventricular refractory period and a ventricular rate time out period;

state controller circuit means responsive to said timing signals for coupling said T wave selection criteria data word from said memory means to said first digital filter means during said refractory period and for coupling said R wave selection criteria data words from said memory means to said first digital filter means during said ventricular rate time out period;

pulse generator circuit means for generating a stimulating pulse on said electrode means of said detector circuit means fails to sense a natural heartbeat before the end of a ventricular rate time out period;

atrial electrode means for sensing an electrical signal representative of atrial cardiac activity;

second digital filter circuit means responsive to the output of said atrial electrode means for detecting a P wave during said ventricular rate time out period; and

circuit means responsive to the detection of a P wave during said ventricular rate time out period for re-establishing said rate time out period to a predetermined time representative of a desired P-R delay interval;

said apparatus being further responsive to the detection of a P wave during said ventricular rate time out period for setting said first digital filter circuit means to detect an R wave during said P-R delay interval for inhibiting the generation of a stimulating pulse and for commencing a new cardiac cycle;

said state controller circuit means being responsive to the end of said P-R delay interval if a natural R wave fails to be detected during such interval to enable said generator circuit means to generate a stimulating pulse.