Insulated gate type field effect transistor having a silicon gate electrode

• US 4,558,338 A
• Filed: 08/15/1983
• Issued: 12/10/1985
• Est. Priority Date: 08/19/1982
• Status: Expired due to Term

• Current Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Original Assignee: NEC Corporation
• Inventors: Sakata, Masanori
• Primary Examiner(s): Edlow, Martin H.
• Assistant Examiner(s): Henn, Terri M.
• Application Number:
  US06/523,656
• Time in Patent Office: 848 Days
• Field of Search: 357/59, 357/23.5, 357/23.9
• US Class Current: 257/387
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4925 with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with only a vertical doping structure or vertical doping variation H01L29/4916
• CPC Class Codes: H01L 29/66575 where the source and drain or source and drain extensions are self-aligned to the sides of the gate H01L29/66606 takes precedence
• CPC Class Codes: Y10S 148/082 Ion implantation FETs/COMs

Abstract

The present invention relates to cross-sectional shape of a silicon gate electrode of an insulated gate field effect transistor. The gate electrode is composed of polycrystalline silicon, and its length, in cross section, gradually increases from the surface contacting to the gate insulating film toward the central portion thereof and then gradually decreases toward the upper surface thereof. The central portion of the polycrystalline silicon has the largest length in the source-drain direction and contains small amount of SiO₂ particles. Relying upon this gate shape, the portion having largest length, can be used as a mask to introduce impurities in a self-aligned manner to form source and drain regions. The thus formed source and drain regions create small capacity relative to the gate electrode. Therefore, a high speed transistor is realized.

Claims

1. An insulated gate type field effect transistor comprising a semiconductor substrate having a semiconductor region of one conductivity type, at least one of source and drain regions of the opposite conductivity formed in said semiconductor region, a channel region abutted against said one of said source and drain regions and extending in its lengthwise direction in said semiconductor region, a gate insulating film formed on said channel region, and a gate electrode formed on said gate insulating film, said gate electrode including a lower layer of polycrystalline silicon attached to said gate insulating film at its bottom surface and being substantially free from silicon dioxide particles, an inner layer of polycrystalline silicon provided on said lower layer and containing silicon dioxide particles therein, and an upper layer of polycrystalline silicon provided on said inner layer, being substantially free from silicon dioxide particles and having an upper surface,

a length of said inner layer in said lengthwise direction of said channel region being larger than that of said lower layer at said bottom surface of said lower layer.

2. An insulated gate type field effect transistor of claim 1, in which the length of said gate electrode increases gradually from said bottom surface toward said inner layer, and decreases gradually from said inner layer toward said upper surface.

3. An insulating gate type field transistor of claim 1, in which said inner layer contains 0.1 to 2.0% by weight of silicon dioxide.

4. An insulated gate type field effect transistor of claim 1, in which said inner layer has the thickness of 50 to 500 angstroms.