Method for maintaining the integrity of a dual microprocessor multiprocessing computing system

• US 4,558,416 A
• Filed: 05/27/1983
• Issued: 12/10/1985
• Est. Priority Date: 05/27/1983
• Status: Expired due to Fees

• Current Assignee: Siemens-Bendix Automotive Electronics LP
• Original Assignee: Allied Corp. (Honeywell International Inc.)
• Inventors: Wright, Danny O., Pauwels, Michael A.
• Primary Examiner(s): Gruber, Felix D.
• Application Number:
  US06/499,115
• Time in Patent Office: 928 Days
• Field of Search: 364/431.11, 364/200, 364/900, 371/9, 371/11, 371/21, 371/15
• US Class Current: 701/114
• CPC Class Codes: F02D 41/2425 Particular ways of programming the data
• CPC Class Codes: F02D 41/266 the computer being backed-up or assisted by another circuit, e.g. analogue
• CPC Class Codes: F02P 15/008 Reserve ignition systems; Redundancy of some ignition devices
• CPC Class Codes: G06F 11/0724 in a multiprocessor or a multi-core unit multiprocessors per se G06F15/80
• CPC Class Codes: G06F 11/076 by exceeding a count or rate limit, e.g. word- or bit count limit
• CPC Class Codes: G06F 11/0763 by bit configuration check, e.g. of formats or tags

Abstract

A dual microprocessor computing system is used to control an engine in a motor vehicle. Each system contains a Personality Programmable Read Only Memory (PPROM) containing system calibration data that is transferred from the PPROM to the read-write memories in the microprocessors. In order to identify each PPROM a byte of memory contains a check sum and a byte of the microprocessor memory contains an identical check sum. During data transfer, the check sums are compared. Also during data transfer, the amount of data being transferred within a predetermined interval is counted both at the transmitter and the receiver memories.

Claims

1. A method for maintaining the integrity of a dual microprocessor multiprocessing computing system having a removable programmable read only memory with an identifying check sum contained therein, the programmable read only memory containing data for tailoring the computing system to a dedicated system, comprising the steps of:

initiating in the second microprocessor and in response to an initializing signal, a timing period having a predetermined time length;

transmitting bit signals from the programmable read only memory through the first microprocessor to the second microprocessor;

counting the number of bit signals being transmitted from the first microprocessor;

counting the number of bit signals being received in the second microprocessor within said time period for generating a received check sum;

comparing the predetermined number with the received check sum; and

then

proceeding with the operation of the multiprocessing computing system when the received check sum and the predetermined number are equal and reinitializing the system after the end of the timing period if the received check sum and the predetermined number are unequal.

2. A method for maintaining the integrity of a dual microprocessor multiprocessing computing system having a removable programmable read only memory with an identifying check sum contained therein, the programmable read only memory containing data for tailoring the computing system to a dedicated system, comprising the steps of:

transmitting bit signals from the programmable read only memory through the first microprocessor to the second microprocessor;

counting the bit signals being transmitted from the first microprocessor for generating a transmitted check sum;

receiving in the second microprocessor the bit signals being transmitted from the first microprocessor;

counting the bit signals being received in the second microprocessor for generating a received check sum;

transmitting the received check sum to the first microprocessor;

comparing in the first microprocessor the transmitted check sum and the received check sum for equality;

proceeding with the operation of the multiprocessing computing system with equality between the transmitted check sum and the received check sum and reinitializing the system if the transmitted check sum is not equal to the received check sum.

3. In a dual microprocessor multiprocessing computing system having a programmable read only memory containing data for a particular application of the computing system, at least two microprocessors each having timer means and a plurality of memories, wherein the first one of the microprocessors is the master microprocessor and operates to synchronize the second microprocessor thereto, a system for maintaining the integrity of the computing system, said system comprising:

means for generating an initializing signal operable to reset the computing system to a base line condition;

means within the programmable read only memory for maintaining a first identifier for indicating the characteristics of the programmable read only memory;

memory means within the first microprocessor for maintaining a second identifier for indicating the correct programmable read only memory to connect to said first microprocessor;

means within the first microprocessor for reading the first identifier;

comparison means for comparing the first identifier with the second identifier; and

means responsive to said comparison means and operable when said identifiers are equivalent to initiate data transmission between the programmable read only memory and the microprocessors.