Memory system for storing analog information

• US 4,558,431 A
• Filed: 12/12/1983
• Issued: 12/10/1985
• Est. Priority Date: 12/10/1982
• Status: Expired due to Fees

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Satoh, Noboru
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US06/560,308
• Time in Patent Office: 729 Days
• Field of Search: 365/45, 365/189, 365/230
• US Class Current: 365/45
• CPC Class Codes: G11C 27/005 with non-volatile charge storage, e.g. on floating gate or MNOS
• CPC Class Codes: G11C 27/02 Sample-and-hold arrangements G11C27/04 takes precedence
• CPC Class Codes: H01L 29/68 controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched

Abstract

The non-volatile semiconductor memory elements having an MIS structure show a hysteresis curve in the gate voltage-the threshold voltage characteristic. The continuously changing region of the hysteresis curve is used to operate the memory elements as analog memories. The input analog signal is applied to the gate electrode of a selected memory element after it is converted to have a voltage within the continuously changing region, to change the threshold voltage of the selected memory element. The changed threshold voltage is read out in read-out operation.

Claims

1. A memory system for storing analog information comprising a memory section including a plurality of non-volatile, insulated-gate field-effect memory transistors, the threshold voltage of said memory transistor being changed continuously in response to the gate voltage thereof so long as said gate voltage is within a predetermined voltage range, an input terminal for receiving an input signal having said analog information, a voltage converter converting said input signal to have a voltage within said predetermined voltage range, a first means for applying said converted input signal to a selected first one of said memory transistors to change the threshold voltage of the selected first memory transistor in accordance the voltage of said converted input signal, and a second means for reading the analog information stored in said memory transistors, said second means including means for detecting the changed threshold voltage of a selected second one of said memory transistors.

2. The memory system as claimed in claim 1, in which said detecting means includes a means for applying a varying voltage to the gate electrode of said selected second memory transistor and means for determining the voltage value at the gate electrode of said selected second memory transistor when a current starts flowing through said selected second memory transistor by said varying voltage.

3. The memory system as claimed in claim 1, wherein each of said memory transistors has a gate insulator of a silicon oxide film and a silicon nitride film deposited on said silicon oxide film.

4. The memory system as claimed in claim 1, wherein said predetermined voltage range is a gate voltage of said memory transistor where said threshold voltage changes linearly but does not change its polarity.

5. The memory system as claimed in claim 2, wherein said second means further includes means for stopping the application of said varying voltage to the gate electrode of said selected second memory transistor when the current starts flowing through said selected second memory transistor.

6. The memory system as claimed in claim 2, further comprising a sampling circuit connected between said input terminal and said voltage converter for sampling said input signal with a predetermined timing.

7. A method for employing a non-volatile semiconductor memory element having a structure of an insulated gate field effect transistor as an analog memory, comprising steps of converting an input signal having analog information to have a voltage in a predetermined range, said predetermined range corresponding to a gate voltage range of said memory element where the threshold voltage of said memory changes linearly in accordance with the voltage applied to the gate electrode of said memory element, applying said converted input signal to said gate electrode of said memory element to memorize said analog information in said input signal into said memory element, and reproducing said analog information from said memory element, said reproducing step including processes of applying a various voltage to said gate electrode of said memory element and deriving said voltage at said gate electrode as an output signal when a current starts flowing through said memory element.

8. The method for using a non-volatile semiconductor memory element as claimed in claim 7, wherein said memory element has a gate insulator of a silicon oxide film and a silicon nitride film deposited on said silicon oxide film.

9. The method for using a non-volatile semiconductor memory element as claimed in claim 7, wherein said reproducing step further comprises a process of stopping the application of said various voltage to said gate electrode when said current starts flowing through said memory element.

10. The method for using a non-volatile semiconductor memory element as claimed in claim 7, wherein said current is detected by a voltage change at the drain electrode of said memory element.

11. A memory system for storing analog information comprising a memory section including a plurality of insulated-gate field-effect memory transistors, a first input terminal for receiving an input signal having said analog information, a voltage converter for converting the voltage of said input signal to a voltage within a predetermined range, said predetermined range corresponding to a range of the gate voltage of said memory transistor which continuously changes the threshold voltage of said memory transistor, said voltage converter being formed of bipolar transistors and passive elements, a second input terminal for receiving an address signal, an address selector for selecting one of said memory transistors in accordance with said address signal, said converted input signal being applied to the gate electrode of said selected memory transistor to change the threshold voltage of said memory transistor, said address selector being formed of insulated-gate field-effect transistors and passive elements, a detection circuit formed of bipolar transistors and passive circuit elements for detecting the changed threshold voltage of said selected memory transistor.

12. The memory system as claimed in claim 11, wherein said detection circuit includes means for applying a varying voltage to the gate electrode of said selected memory transistor, means for detecting that a current starts flowing through said selected memory transistor by said varying voltage, and means for determining the voltage value of said varying voltage at the gate electrode of said selected memory transistor which causes said current to flow.

13. A memory system as claimed in claim 11, wherein each of said memory transistors has a gate insulator of a silicon oxide film and a silicon nitride film deposited on said silicon oxide film.

14. A memory system as claimed in claim 11, further comprising a sampling circuit inserted between said first input terminal and said voltage converter for sampling said input signal with a predetermined timing, said sampling circuit being formed of bipolar transistors and passive elements.

15. A memory system as claimed in claim 14, further comprising an amplifier coupled to said detection circuit for amplifying the voltage of the determined voltage value.