Antitheft system with digitally coded signal

• US 4,559,529 A
• Filed: 04/15/1985
• Issued: 12/17/1985
• Est. Priority Date: 06/29/1983
• Status: Expired due to Term

• Current Assignee: 3SI Security Systems, Inc. (3SI Holdco, Inc.)
• Original Assignee: U.S. Currency Protection Corp. (3SI Holdco, Inc.)
• Inventors: Bernhardt, Terry L.
• Primary Examiner(s): Swann, III, Glen R.
• Application Number:
  US06/723,551
• Time in Patent Office: 246 Days
• Field of Search: 340/571, 340/572, 340/568
• US Class Current: 340/571
• CPC Class Codes: G08B 13/2431 Tag circuit details
• CPC Class Codes: G08B 13/2474 Antenna or antenna activator geometry, arrangement or layout loop antennae H01Q1/22
• CPC Class Codes: G08B 13/2477 Antenna or antenna activator circuit
• CPC Class Codes: G08B 13/2482 EAS methods, e.g. description of flow chart of the detection procedure
• CPC Class Codes: G08B 13/2488 Timing issues, e.g. synchronising measures to avoid signal collision, with multiple emitters or a single emitter and receiver

Abstract

A transmitter emits a pulsed radio signal and a digitally encoded radio signal near each exit of a protected premises. Monitored articles carry a receiver having a first circuit for receiving the pulsed signal, a power source, and a power switch for coupling the power source to a second circuit on detection of the pulsed signal. The second circuit receives the digitally encoded signal as multiple, serially-transmitted code bits. It also contains a clock for generating timing signals synchronized by the pulsed signal in order to distinguish a plurality of code bit intervals. A processor, an associated memory, and an address counter compare the digitally encoded signal with a stored bit pattern. On receiving an improper code bit, the processor causes the power switch to decouple the power source from the second circuit to conserve power. If the received signal matches the stored bit pattern, power is maintained to the second circuit. Alarm circuitry is triggered by overflow from the address counter. The address counter is reset each time the pulsed signal is received and thus produces no overflow, but when the article is removed from the protected premises, the address counter is allowed to overflow, triggering the alarm circuit.

Claims

1. A security system for detecting the removal of an article from a premises to be protected, the protected premises including at least one exit through which the article may be removed from the protected premises, said security system comprising in combination:

(A) a transmitter for transmitting at least one signal in the vicinity of said exit, said signal being transmitted as an electromagnetic radio wave of a predetermined frequency and being transmitted as a plurality of serially coded bits, said serially coded bits being transmitted by said transmitter during a corresponding plurality of successive code bit intervals;

(B) receiver means carried by said article, said receiver means including;

i. a receiver for detecting the presence of said signal, said receiver including a filter for passing signals of said predetermined frequency, said receiver being adapted to receive said serially coded bits when said article is brought into the vicinity of said exit;

ii. processing means for storing a pattern of code bits and being coupled to said receiver for comparing the serially coded bits received by said receiver with the stored code bits to determine whether they match one another, said processing means providing an output signal when said serially coded bits match the stored code bits;

iii. clocking means for providing clock signals to said processing means to distinguish the plurality of successive code bit intervals; and

iv. alarm means electrically coupled to said processing means and responsive to said output signal for creating an alarm to assist in the recovery of the removed article; and

(C) a power supply carried by said article and electrically coupled to said receiver means for supplying electrical power thereto.

2. A security system as recited by claim 1 wherein said processing means includes:

(A) a microprocessor having a plurality of instruction input terminals for receiving a multiple-bit instruction code representative of an operation to be performed by said microprocessor, said microprocessor further including at least one data port for receiving data and including a clock terminal for receiving a first clock signal to synchronize the performance of operations within said microprocessor and to synchronize the receipt of data by said microprocessor;

(B) an addressable memory having a plurality of address input terminals for receiving an address and having a plurality of output terminals at least some of which are coupled to the instruction input terminals of said microprocessor for providing an instruction code thereto;

(C) an address counter having a clock terminal for receiving a second clock signal, said address counter having a plurality of output terminals at least some of which are coupled to the address input terminals of said addressable memory for providing an address thereto, said address counter causing the address provided by the output terminals thereof to be sequentially modified each time said second clock signal is received by the clock terminal of said address counter; and

(D) coupling means for selectively coupling said receiver to the data port of said microprocessor for allowing said microprocessor to compare the serially coded bits received by the first receiver to the corresponding stored code bits.

3. A security system as recited by claim 2 wherein

(A) said addressable memory includes a data terminal for providing data representative of stored code bits therein, said addressable memory including at least one selector output terminal for providing a selector signal;

and

(B) said coupling means includes a first input terminal coupled to the data terminal of said addressable memory for receiving the stored code bits, a second input terminal coupled to said receiver for receiving the serially coded bit received during a particular code bit interval, a third input terminal for receiving said selector signal, and an output terminal coupled to the data port of said microprocessor for selectively coupling the stored code bits and the received serially coded bits to said microprocessor.

4. A security system as recited by claim 2 wherein said clocking means includes synchronizing means for generating a synchronizing signal, said clocking means being responsive to said synchronizing signal for synchronizing the clock signals provided thereby to the serially-coded signal transmitted by said transmitter.

5. A security system as recited by claim 4 wherein:

(A) said transmitter transmits a second signal in the vicinity of said exit, said second signal being transmitted as an electromagnetic radio wave of a second predetermined frequency and being transmitted as a periodic pulse; and

(B) said receiver means includes a second receiver for detecting said second signal transmitted by said transmitter, said synchronizing means being coupled to said second receiver and being responsive to the detection of said second signal for generating said synchronizing signal.

6. A security system for detecting the removal of an article from a premises to be protected, the protected premises including at least one exit through which the article may be removed from the protected premises, said security system comprising in combination:

(A) a transmitter for transmitting at least one radio signal of a predetermined frequency in the vicinity of said exit; and

(B) a receiver carried by said article for detecting the presence of said radio signal and including a filter for passing signals of said predetermined frequency; and

(C) a power supply carried by said article and electrically coupled to said receiver for supplying electrical power thereto;

(D) said filter of said receiver including;

i. a first current programmable operational amplifier having an inverting input terminal and an output terminal and including a first feedback resistor of a first magnitude coupled therebetween;

ii. a second current programmable operational amplifier having an inverting input terminal coupled to the output of said first operational amplifier, said second operations amplifier having an output terminal; and

iii. A second feedback resistor coupled between the output terminal of said second operational amplifier and the inverting input terminal of said first operational amplifier, the ratio of the magnitude of the first feedback resistor to the magnitude of the second feedback resistor being near unity to increase the selectivity of said filter; and

iv. said first and second operational amplifiers are programmed to operate at substantially minimum current levels to minimize power drawn from said power supply and to minimize the bandwidth of the gain provided by each of said first and second operational amplifiers to increase the selectivity of said filter and to decrease the tendency of said filter to oscillate.