CMOS Charge pump free of parasitic injection

• US 4,559,548 A
• Filed: 04/02/1982
• Issued: 12/17/1985
• Est. Priority Date: 04/07/1981
• Status: Expired due to Term

• Current Assignee: Tokyo Shibaura Denki Kabushiki Kaisha (Toshiba Corporation)
• Original Assignee: Tokyo Shibaura Denki Kabushiki Kaisha (Toshiba Corporation)
• Inventors: Iizuka, Tetsuya, Hara, Hisashi
• Primary Examiner(s): Larkins, William D.
• Application Number:
  US06/364,639
• Time in Patent Office: 1,355 Days
• Field of Search: 357/42, 357/51, 307/296 A, 307/296 R, 307/304, 363/59, 363/60, 365/226
• US Class Current: 257/299
• CPC Class Codes: G05F 3/205 Substrate bias-voltage generators for static stores G11C5/146
• CPC Class Codes: H01L 27/0222 Charge pumping, substrate bias generation structures

Abstract

A charge pump bias generator constructed of P channel MOSFETs in an N type substrate is used to provide a negative bias to a P well containing active N-channel MOSFET circuit elements to reverse bias the N type source to P well junctions. Since the charge pump uses P channel FETs in an N substrate with the N substrate connected to the positive power supply, parasitic minority carrier injection by the charge pump is prevented.

Claims

1. A substrate bias generator comprising:

a semiconductor substrate;

a first semiconductor region of a first conductivity type existing in said semiconductor substrate, said semiconductor region supplied with a first potential;

a capacitive element formed in said first semiconductor region, said capacitive element including a second semiconductor region as a first electrode and a conductive means formed on said second semiconductor region as a second electrode with an insulation film interposed therebetween;

a MOS transistor formed in said first semiconductor region serving as a first rectifying element, said MOS transistor including source and drain regions of a second conductivity type so as to establish a PN junction between said semiconductor region and said source and drain regions, said MOS transistor further including a gate electrode formed on said first semiconductor region between said source and drain regions with an insulation film interposed therebetween;

a second rectifying element formed in said first semiconductor region having first and second terminals, said first terminal supplied with a second potential;

a third semiconductor region of the second conductivity type existing in said semiconductor substrate, in which circuit elements are formed;

voltage supply means for supplying an AC voltage to one of said first and second electrodes of said capacitive element;

first means for connecting together the other one of said first and second electrodes of said capacitive element, said gate electrode of said MOS transistor, one of said source and drain regions of said MOS transistor, and said second terminal of said rectifying element;

second means for connecting said third semiconductor region to the other one of said source and drain regions of said MOS transistor, whereby said PN junction formed between said first semiconductor region and said source and drain regions is reversebiased during operation of said substrate bias generator.

2. A substrate bias generator according to claim 1, wherein said first semiconductor region and said semiconductor substrate have the same conductivity types.

3. A substrate bias generator according to claim 2, wherein said first conductivity type is an N type and said second conductivity type is a P type.

4. A substrate bias generator according to claim 3, wherein said third semiconductor region is a P-well formed in said semiconductor substrate.

5. A substrate bias generator according to claim 1, wherein said second semiconductor region is of a second conductivity type and is integral with one of the said source and drain regions of said MOS transistor.

6. A substrate bias generator according to claim 5, wherein said AC voltage supply means is connected to said conductive means of said capacitive element.

7. A substrate bias generator according to claim 1, wherein said second rectifying element is a MOS transistor having one of said source and drain regions and a gate electrode supplied with the second reference potential, said source and drain regions being formed in said first semiconductor region and having the second conductivity type.

8. A substrate bias generator according to claim 1, wherein said second rectifying element is a diode including a fourth semiconductor region connected to said second semiconductor region of said capacitive element and one of the source and drain regions of said MOS transistor and a fifth semiconductor region of the first conductivity type, said fifth semiconductor region being supplied with the second potential.

9. A substrate bias generator according to claim 1, wherein the other one of said source and drain regions of said MOS transistor is formed integrally with said third semiconductor region.