Content-addressable memory module with associative clear

• US 4,559,618 A
• Filed: 09/13/1982
• Issued: 12/17/1985
• Est. Priority Date: 09/13/1982
• Status: Expired due to Term

• Current Assignee: Data General Corp. (Dell Technologies Inc.)
• Original Assignee: Data General Corp. (Dell Technologies Inc.)
• Inventors: Bowden, Paul, Houseman, David L.
• Primary Examiner(s): Popek, Joseph A.
• Application Number:
  US06/417,801
• Time in Patent Office: 1,191 Days
• Field of Search: 365/49, 365/230
• US Class Current: 365/49.15
• CPC Class Codes: G06F 16/90339 by using parallel associative memories or content-addressable memories

Abstract

A content-addressable memory module which performs an associative clear operation in response to a clear signal provided on a clear line. The associative clear operation simultaneously clears all registers in the content-addressable memory module whose contents match bits in a pattern input to the content-addressable memory module. A mask input along with the pattern determines which bits of the pattern are significant for the match. Each register in the content-addressable memory module has a bidirectional match line associated with it. A register'"'"'s bidirectional match line carries a match signal only if that register contains data matching the pattern bits specified by the mask and the bidirectional match line is receiving a match signal from an external source. Clearing logic associated with each register clears the register when a clear signal appears on the clear line while the register'"'"'s bidirectional match line is carrying a match signal. In content-addressable memories constructed of such content-addressable memory modules, memory match lines connect match lines associated with a number of registers. The memory match line and all of the match lines connected to it carry match signals only if each of the registers associated with the match lines contains data matching the pattern and mask input to the content-addressable memory module containing the register. The content-addressable memory module further contains logic allowing the use of encoded addresses to address individual registers in the content-addressable memory module.

Claims

1. A content-addressable memory module comprising:

(1) a plurality of register means, each register means of said plurality of register means containing one stored item of data;

(2) means for receiving a pattern item of data;

(3) a plurality of means for detecting said register means containing said stored items of data matching said pattern item of data, each one of said plurality of match detection means being associated with one said register means, being responsive to said stored item of data contained in said one said register means and to said pattern item of data, and providing a match signal when said one said register means associated with said one match detection means contains said stored item of data matching said pattern item of data; and

(4) a plurality of bidirectional match signalling means for providing said match signal from said content-addressable memory module and receiving said match signal from an external source, each one of said bidirectional match signalling means being associated with one of said register means and responsive to said match signal from said match detection means associated with said associated register means and to said match signal from said external source, and acting to provide said match signal only when simultaneously receiving said match signal from said associated match detection means and from said external source.

2. In the content-addressable memory module of claim 1, and wherein

said bidirectional match signalling means is a match line connected to said associated match detection means for providing and receiving a match state and a no-match state;

said match signal is said match state; and

said match line is connected to an open-collector driver circuit in said associated match detection means and said open-collector driver circuit places said connected match line in said no match state unless said stored item of data in said register means associated with said match detection means matches said pattern item of data.

3. In the content-addressable memory module of claim 2, and wherein:

said match state is a high voltage and

said no match state is a low voltage.

4. In the content-addressable memory module of claim 3, and wherein:

a pattern sequence of bits in said pattern item of data corresponds to a certain sequence of bits in each one of said stored items of data, said match detection means is responsive to said pattern sequence of bits and to said certain sequence of bits, and said stored item of data matches said pattern item of data when said bits in said certain sequence match said bits in said pattern sequence.

5. In the content-addressable memory module of claim 4, and wherein:

said content-addressable memory module further includes means for receiving a masking item of data for specifying said pattern sequence of bits and

said match detection means is further connected to said masking item receiving means and is responsive to said masking item of data.

6. In the content-addressable memory module of claim 5, and wherein:

said masking item of data further specifies a non-pattern sequence of bits in said pattern item of data;

said stored items of data further contain a second certain sequence of bits corresponding to said non-pattern sequence of bits; and

one said stored item of data matches said pattern item of data when said first certain sequence of bits matches said pattern sequence of bits, regardless of the values of bits in said second certain sequence of bits.

13. In the content-addressable memory of claim 7, 10, or 1, and wherein said content-addressable memory module further comprises:

address receiving means connected to said plurality of register means for receiving an encoded address specifying an addressed register means of said plurality of register means from an external source, decoding said encoded address to generate an address signal for said addressed register means specified by said encoded address, and providing said address signal to said addressed register means, each register means of said plurality of register means being responsive to said address signal.

14. In the content-addressable memory module of claim 13 and wherein:

said address receiving means includes

(a) encoded address receiving means for receiving an encoded address specifying said addressed register means from said external source;

(b) decoding means connected to said encoded address receiving means and responsive to said encoded address for decoding said encoded address and generating said address signal for said addressed register means; and

(c) means connected to said decoding means and said plurality of register means for providing said address signal to said addressed register means.

15. In the content-addressable memory module of claim 7, 10, or 1, and wherein said content-addressable memory module further comprises:

data input means for receiving an input item of data from an external source;

means for receiving an address specifying an addressed register means of said plurality of register means from an external source and providing an address signal for said addressed register means;

data output means for outputting one said stored item of data from said content-addressable memory module;

means for receiving an output enable signal from an external source;

means for receiving a write enable signal from an external source;

data writing means connected to said plurality of register means, said address receiving means, said data input means, and said write enable signal receiving means for setting said stored item of data in said addressed register means to the value of said input data item in response to said input item of data, said address signal, and said write enable signal;

data reading means connected to said plurality of register means, said address receiving means, said data output means, and said output enable signal receiving means for providing said stored item of data in said addressed register means to said data output means in response to said address signal and said output enable signal.

7. A content-addressable memory module comprising:

(1) a plurality of register means, each register means of said plurality of register means containing one stored item of data;

(2) means for receiving a pattern item of data;

(3) means for receiving a clear signal specifying that certain ones of said plurality of register means are to be cleared, said certain ones being said register means containing said stored items of data matching said pattern item of data; and

(4) means for simultaneously clearing said certain ones of said register means, said simultaneous clearing means being connected to said plurality of register means, to said pattern receiving means, and to said clear signal receiving means and responding to said stored item of data, said pattern item of data, and said clear signal by simultaneously clearing said certain ones of said register means on receipt of said clear signal in said clear signal receiving means;

wherein;

a pattern sequence of bits in said pattern item of data corresponds to a certain sequence of bits in each one of said stored items of data and said stored item of data matches said pattern item of data when said bits in said certain sequence match said bits in said pattern sequence;

and wherein said simultaneous clearing means includes;

(a) a plurality of means for detecting said register means containing said stored items of data matching said pattern item of data, each one of said plurality of match detection means being associated with one said register means and being responsive to said stored item of data contained in said one said register means and to said pattern item of data, and each one of said plurality of match detection means acting to provide a match signal when said one said register means associated with said one match detection means contains said stored item of data matching said pattern item of data;

(b) means for providing a register clearing signal specifying any one of said register means in response to said clear signal and to said match signal; and

(c) a plurality of means for clearing said register means, each one of said register clearing means being associated with one of said register means and being responsive to said register clearing signal.

8. In the content-addressable memory module of claim 7, and wherein:

said content-addressable memory module further includes a plurality of bidirectional match signalling means for providing said match signal from said content-addressable memory module, receiving said match signal from an external source, and providing said match signal to said register clearing signal providing means, each bidirectional match signalling means of said plurality of bidirectional match signalling means being associated with one register means of said plurality of register means and being connected to said match detection means associated with said associated register means and to said register clearing signal providing means, and each said bidirectional match signalling means providing said match signal to said register clearing signal providing means only when said bidirectional match signalling means is simultaneously receiving said match signal from said connected match detection means and from said external source.

9. In the content-addressable memory module of claim 8, and

wherein:

said bidirectional match signalling means is a match line connected to said match detection means and to said register clearing signal providing means;

said match line provides and receives a match state and a no-match state;

said match signal is said match state; and

each said match line is connected to an open-collector driver circuit in said associated match detection means and said open-collector driver circuit places said connected match line in said no match state unless said stored item of data in said register means associated with said match detection means matches said pattern item of data.

10. A content-addressable memory module comprising:

(1) a plurality of register means, each register means of said plurality of register means containing one stored item of data;

(2) means for receiving a pattern item of data;

(3) means for receiving a clear signal specifying that certain ones of said plurality of register means are to be cleared, said certain ones being said register means containing said stored items of data matching said pattern item of data; and

(4) means for simultaneously clearing said certain ones of said register means, said simultaneous clearing means being connected to said plurality of register means, to said pattern receiving means, and to said clear signal receiving means and responding to said stored item of data, said pattern item of data, and said clear signal by simultaneously clearing said certain ones of said register means on receipt of said clear signal in said clear signal receiving means;

wherein;

a pattern sequence of bits in said pattern item of data corresponds to a certain sequence of bits in each one of said stored items of data and said stored item of data matches said pattern item of data when said bits in said certain sequence match said bits in said pattern sequence.

and wherein;

said content-addressable memory further includes means for receiving a masking item of data for specifying said pattern sequence of bits and said simultaneous clearing means is further connected to said masking item receiving means and is responsive to said masking item of data;

and wherein;

said masking item of data further specifies a non-pattern sequence of bits in said pattern data item;

said stored items of data further contain a second certain sequence of bits corresponding to said non-pattern sequence of bits; and

one said said stored item of data matches said pattern data item when said first certain sequence of bits matches said pattern sequence of bits, regardless of the values of bits in said second certain sequence of bits;

and wherein;

said masking item of data specifies all said bits in said pattern item of data as said non-pattern sequence of bits, whereby all said stored items of data match said pattern item of data, all said register means in said plurality of register means are said certain ones of said plurality of register means, and said simultaneous clearing means simultaneously clears all said register means in said plurality of register means upon receipt of said clear signal in said clear signal receiving means.

11. In the content-addressable memory module of claim 10, and wherein:

said simultaneous clearing means further includes

(a) a plurality of means for detecting said register means containing said stored items of data matching said pattern item of data, each one of said plurality of match detection means being associated with one said register means, being responsive to said stored item of data contained in said one said register means, to said pattern item of data, and to said mask item of data, and providing a match signal when said one said register means associated with said one match detection means contains said stored item of data matching said pattern item of data,

(b) means for providing a register clearing signal to any one of said register means in response to said clear signal and to said match signal,

(c) a plurality of means for clearing said register means, each one of said register clearing means being associated with one of said register means and being responsive to said register clearing signal.

12. In the content-addressable memory module of claim 11, and wherein:

said content-addressable memory module further includes a plurality of bidirectional match signalling means for providing said match signal from said content-addressable memory module, receiving said match signal from an external source, and providing said match signal to said register clearing signal providing means, each bidirectional match signalling means of said plurality of bidirectional match signalling means being associated with one register means of said plurality of register means and being connected to said match detection means associated with said associated register means and to said register clearing signal providing means, and each said bidirectional match signalling means providing said match signal to said register clearing signal providing means only when said bidirectional match signalling means is simultaneously receiving said match signal from said connected match detection means and from said external source.

16. A content-addressable memory comprising:

(1) a plurality of content-addressable memory modules, each content-addressable memory module of said plurality of content-addressable memory modules including

(a) a plurality of register means, each register means of said plurality of register means containing one stored item of data;

(b) means for receiving a pattern item of data;

(c) means for receiving a clear signal specifying that certain ones of said plurality of register means are to be cleared, said certain ones being said register means containing said stored items of data matching said pattern item of data; and

(d) means for simultaneously clearing said certain ones of said register means, said simultaneous clearing means being connected to said plurality of register means, to said pattern item receiving means, and to said clear signal receiving means and responding to said stored item of data, said pattern item of data, and said clear signal by simultaneously clearing said certain ones of said register means on receipt of said clear signal in said clear signal receiving means; and

(2) memory clear signal providing means connected to said clear signal receiving means in each one of said plurality of memory modules for simultaneously providing said clear signal to all said content-addressable memory modules in said plurality of content-addressable memory modules;

wherein;

said simultaneous clearing means includes

(i) a plurality of means for detecting said register means containing said stored items of data matching said pattern item of data, each one of said plurality of match detection means being associated with one said register means and being responsive to said stored item of data contained in said one said register means and to said pattern item of data, and each one of said plurality of match detection means acting to provide a match signal when said one said register means associated with said one match detection means contains said stored item of data matching said pattern item of data;

(ii) means for providing a register clearing signal to any one of said register means in response to said clear signal and to said match signal; and

(iii) a plurality of means for clearing said register means, each one of said register clearing means being associated with one of said register means and being responsive to said register clearing signal;

said content-addressable memory module further includes a plurality of bidirectional match signalling means for providing said match signal from said content-addressable memory module, receiving said match signal from an external source, and providing said match signal to said register clearing signal providing means, each bidirectional match signalling means of said plurality of bidirectional match signalling means being associated with one register means of said plurality of register means and being connected to said match detection means associated with said associated register means and to said register clearing signal providing means, and each said bidirectional match signalling means providing said match signal to said register clearing signal providing means only when said bidirectional match signalling means in simultaneously receiving said match signal from said connected match detection means and from said external source; and

said content-addressable memory further includes a plurality of memory match signalling means for receiving said match signal from said bidirectional match signalling means and serving as said external source for providing said match signal to said bidirectional match signalling means, each one of said memory match signalling means corresponding to one of said bidirectional match signalling means, being connected to said corresponding said match signalling means in each of said content-addressable memory modules, and providing said match signal to said connected bidirectional match signalling means only when all of said connected bidirectional match signalling means are providing said match signal;

whereby said content-addressable memory responds to said clear signal provided by said memory clear signal providing means by clearing said register means only when said register means contain said stored items of data matching said pattern item of data and said register means are associated with said bidirectional match signalling means which are receiving said match signal from said memory match signalling means.

17. In the content-addressable memory of claim 16, and wherein said content-addressable memory further comprises:

an additional plurality of said content-addressable memory modules; and

an additional said memory clear signal providing means connected to said clear signal receiving means in each one of said additional plurality of memory modules,

and wherein each one of said plurality of memory match signalling means is further connected to said corresponding bidirectional match signalling means in each content-addressable memory module of said additional plurality of content-addressable memory modules.

18. In the content-addressable memory of claim 16, and wherein said content-addressable memory further comprises:

an additional plurality of said content-addressable memory modules; and

an additional plurality of memory match signalling means, each one of said additional plurality of memory match signalling means being connected to said corresponding said match signalling means in each of said content-addressable memory modules of said additional plurality of content-addressable memory modules; and

wherein said memory clear signal providing means is further connected to said clear signal receiving means in each content-addressable memory module of said additional plurality of memory modules.

19. In the content-addressable memory of claim 16, and wherein:

a pattern sequence of bits in said pattern item of data corresponds to a certain sequence of bits in each one of said stored items of data and said stored item of data matches said pattern item of data when said bits in said certain sequence match said bits in said pattern sequence.

20. In the content-addressable memory of claim 19, and wherein:

said simultaneous clearing means includes

(i) a plurality of means for detecting said register means containing said stored items of data matching said pattern item of data, each one of said plurality of match detection means being associated with one said register means and being responsive to said stored item of data contained in said one said register means and to said pattern sequence of bits, and each one of said plurality of match detection means acting to provide a match signal when said one said register means associated with said one match detection means contains said stored item of data matching said pattern item of data,

(ii) means for providing a register clearing signal to any one of said register means in response to said clear signal and to said match signal, and

(iii) a plurality of means for clearing said register means, each one of said register clearing means being associated with one of said register means and being responsive to said register clearing signal;

said content-addressable memory module further includes a plurality of bidirectional match signalling means for providing said match signal from said content-addressable memory module, receiving said match signal from an external source, and providing said match signal to said register clearing signal providing means, each bidirectional match signalling means of said plurality of bidirectional match signalling means being associated with one register means of said plurality of register means and being connected to said match detection means associated with said associated register means and to said register clearing signal providing means, and each said bidirectional match signalling means providing said match signal to said register clearing signal providing means only when said bidirectional match signalling means is simultaneously receiving said match signal from said connected match detection means and from said external source; and

said content-addressable memory further includes a plurality of memory match signalling means for receiving said match signal from said bidirectional match signalling means and serving as said external source for providing said match signal to said bidirectional match signalling means, each one of said memory match signalling means corresponding to one of said bidirectional match signalling means, being connected to said corresponding said match signalling means in each of said content-addressable memory modules, and providing said match signal to said connected bidirectional match signalling means only when all of said connected bidirectional match signalling means are providing said match signal,

whereby said content-addressable memory responds to said clear signal provided by said memory clear signal providing means by clearing said register means only when said register means contain said stored items of data matching said pattern item of data and said register means are associated with said bidirectional match signalling means which are receiving said match signal from said memory match signalling means.

21. In the content-addressable memory of claim 19, and wherein:

said content-addressable memory module further includes means for receiving a masking item of data for specifying said pattern sequence of bits and

said simultaneous clearing means is further connected to said masking item receiving means and is responsive to said masking item of data.

22. In the content-addressable memory of claim 21, and wherein:

said masking item of data further specifies a non-pattern sequence of bits in said pattern data item;

said stored items of data further contain a second certain sequence of bits corresponding to said non-pattern sequence of bits; and

one said stored item of data matches said pattern item of data when said first certain sequence of bits matches said pattern sequence of bits, regardless of the values of bits in said second certain sequence of bits.

23. In the content-addressable memory of claim 22, and wherein:

said masking item of data specifies all said bits in said pattern item of data as said non-pattern sequence of bits,

whereby all said stored items of data match said pattern item of data, all said register means in said plurality of register means are said certain ones of said plurality of register means, and said simultaneous clearing means simultaneously clears all said register means in said plurality of register means upon receipt of said clear signal in said clear signal receiving means.

24. In the content-addressable memory module of claim 21, and wherein:

said simultaneous clearing means further includes

(i) a plurality of means for detecting said register means containing said stored items of data matching said pattern item of data, each one of said plurality of match detection means being associated with one said register means, being responsive to said stored item of data contained in said one said register means, to said pattern item of data, and to said mask item of data, and providing a match signal when said one said register means associated with said one match detection means contains said stored item of data matching said pattern item of data,

(ii) means for providing a register clearing signal to any one of said register means in response to said clear signal and to said match signal, and

(iii) a plurality of means for clearing said register means, each one of said register clearing means being associated with one of said register means and being responsive to said register clearing signal;

said content-addressable memory module further includes a plurality of bidirectional match signalling means for providing said match signal from said content-addressable memory module, receiving said match signal from an external source, and providing said match signal to said register clearing signal providing means, each bidirectional match signalling means of said plurality of bidirectional match signalling means being associated with one register means of said plurality of register means and being connected to said match detection means associated with said associated register means and to said register clearing signal providing means, and each said bidirectional match signalling means providing said match signal to said register clearing signal providing means only when said bidirectional match signalling means is simultaneously receiving said match signal from said connected match detection means and from said external source; and

said content-addressable memory further includes a plurality of memory match signalling means for receiving said match signal from said bidirectional match signalling means and serving as said external source for providing said match signal to said bidirectional match signalling means, each one of said memory match signalling means corresponding to one of said bidirectional match signalling means, being connected to said corresponding said match signalling means in each of said content-addressable memory modules, and providing said match signal to said connected bidirectional match signalling means only when all of said connected bidirectional match signalling means are providing said match signal,

whereby said content-addressable memory responds to said clear signal provided by said memory clear signal providing means by clearing said register means only when said register means contain said stored items of data matching said pattern item of data and said register means are associated with said bidirectional match signalling means which are receiving said match signal from said memory match signalling means.

25. In the content-addressable memory of claim 24, and wherein said content-addressable memory further comprises:

an additional plurality of said content-addressable memory modules; and

an additional said memory clear signal providing means connected to said clear signal receiving means in each one of said additional plurality of memory modules,

and wherein each one of said plurality of memory match signalling means is further connected to said corresponding bidirectional match signalling means in each content-addressable memory module of said additional plurality of content-addressable memory modules.

26. In the content-addressable memory of claim 24, and wherein said content addressable memory further comprises:

an additional plurality of said content-addressable memory modules; and

an additional plurality of memory match signalling means, each one of said additional plurality of memory match signalling means being connected to said corresponding said match signalling means in each of said content-addressable memory modules of said additional plurality of content-addressable memory modules; and

wherein said memory clear signal providing means is further connected to said clear signal receiving means in each one of said additional plurality of memory modules.

36. In the content-addressable memory of claim 16, 19, 21, or 27, and wherein:

said content-addressable memory module further includes

address receiving means connected to said plurality of register means for receiving an encoded address specifying an addressed register means of said plurality of register means from an external source, decoding said encoded address to generate an address signal for said addressed register means specified by said encoded address, and providing said address signal to said addressed register means, each register means of said plurality of register means being responsive to said address signal; and

(2) memory register address providing means connected to each said address receiving means in said plurality of memory modules for simultaneously providing said encoded address to said address receiving means in each one of said plurality of memory modules,

whereby said encoded address provided by said memory register address providing means specifies a memory register made up of said addressed register means in each one of said plurality of memory modules.

37. In the content-addressable memory of claim 17, 18, 25, 26, 28, or 35, and wherein:

each content-addressable memory module of said plurality of content-addressable memory modules and of said additional plurality of content-addressable memory modules further includes address receiving means connected to said plurality of register means for receiving an encoded address specifying an addressed register means of said plurality of register means from an external source, decoding said encoded address to generate an address signal for said addressed register means specified by said encoded address, and providing said address signal to said addressed register means, each register means of said plurality of register means being responsive to said address signal; and

said content-addressable memory further includes memory register address providing means connected to each said address receiving means in said plurality of memory modules and to said address receiving means in said additional plurality of memory modules for simultaneously providing said encoded address to said address receiving means in each one of said plurality of memory modules and in each one of said additional plurality of memory modules.

38. In the content-addressable memory of claim 17, 18, 25, 26, 28, or 35, and wherein:

each content-addressable memory module of said plurality of content-addressable memory modules and of said additional plurality of content-addressable memory modules further includes address receiving means connected to said plurality of register means for receiving an encoded address specifying an addressed register means of said plurality of register means from an external source, decoding said encoded address to generate an address signal for said addressed register means specified by said encoded address, and providing said address signal to said addressed register means, each register means of said plurality of register means being responsive to said address signal; and

said content-addressable memory further includes

memory register address providing means connected to each said address receiving means in said plurality of memory modules for simultaneously providing said encoded address to said address receiving means in each one of said plurality of memory modules; and

additional memory register address providing means connected to each said address receiving means in said additional plurality of memory modules for simultaneously providing an additional said encoded address to said address receiving means in each one of said additional plurality of memory modules.

27. A content-addressable memory comprising:

(1) a plurality of content-addressable memory modules, each one of said plurality of content-addressable memory modules including

(a) a plurality of register means, each register means of said plurality of register means containing one stored item of data;

(b) means for receiving a pattern item of data;

(c) a plurality of means for detecting said register means containing said stored items of data matching said pattern item of data, each one of said plurality of match detection means being associated with one said register means, being responsive to said stored item of data contained in said one said register means and to said pattern item of data, and providing a match signal when said one said register means associated with said one match detection means contains said stored item of data matching said pattern item of data; and

(d) a plurality of bidirectional match signalling means for providing said match signal from said content-addressable memory module and receiving said match signal from an external source, each one of said bidirectional match signalling means being associated with one of said register means and responsive to said match signal from said match detection means associated with said associated register means and to said match signal from said external source, and acting to provide said match signal only when simultaneously receiving said match signal from said associated match detection means and from said external source; and

(2) a plurality of memory match signalling means for receiving said match signal from said bidirectional match signalling means and serving as said external source for providing said match signal to said bidirectional match signalling means, each one of said memory match signalling means corresponding to one of said bidirectional match signalling means, being connected to said corresponding said match signalling means in each of said content-addressable memory modules, and providing said match signal to said connected bidirectional match signalling means only when all of said connected bidirectional match signalling means are providing said match signal.

28. In the content-addressable memory of claim 27, and wherein said content-addressable memory further comprises:

an additional plurality of said content-addressable memory modules; and

an additional plurality of said memory match signalling means, each one of said additional plurality of memory match signalling means being connected to said corresponding said match signalling means in each of said content-addressable memory modules of said additional plurality of content-addressable memory modules.

29. In the content-addressable memory of claim 27, and wherein:

said bidirectional match signalling means is a match line connected to said match detection means and clearing signal providing means;

said memory match signalling means is a memory match line connected to a corresponding said match line in each one of said content-addressable memory modules;

said match line and said memory match line provide and receive a match state and a no-match state;

said match signal is said match state; and

each said match line is connected to to an open-collector driver circuit in said associated match detection means and said open-collector driver circuit places said connected match line and said connected memory match line in said no match state unless said stored item of data in said register means associated with said match detection means matches said pattern item of data.

30. In the content-addressable memory of claim 29, and wherein:

said match state is a high voltage and said no match state is a low voltage.

31. In the content-addressable memory of claim 30, and wherein:

a pattern sequence of bits in said pattern item of data corresponds to a certain sequence of bits in each one of said stored items of data, said match detection means is responsive to said pattern sequence of bits and to said certain sequence of bits, and said stored item of data matches said pattern item of data when said bits in said certain sequence match said bits in said pattern sequence.

32. In the content-addressable memory module of claim 31, and wherein:

said content-addressable memory module further includes means for receiving a masking item of data for specifying said pattern sequence of bits and

said match detection means is further connected to said masking item receiving means and is responsive to said masking item of data.

33. In the content-addressable memory module of claim 32, and wherein:

said masking item of data further specifies a non-pattern sequence of bits in said pattern data item;

said stored items of data further contain a second certain sequence of bits corresponding to said non-pattern sequence of bits; and

one said stored item of data matches said pattern item of data when said first certain sequence of bits matches said pattern sequence of bits, regardless of the values of bits in said second certain sequence of bits.

34. In the content-addressable module of claim 33, and wherein:

said masking item of data specifies all said bits in said pattern item of data as said non-pattern sequence of bits,

whereby said memory match line is in said match state when first certain memory modules of said plurality of memory modules receive said masking items of data specifying all said bits in said pattern items of data received by said first certain memory modules as said non-pattern bits, second certain memory modules of said plurality of memory modules receive said masking items not specifying all said bits in said pattern item of data as said bits, and said stored items of data in said register means associated with said memory match lines in said second certain memory modules match said pattern items received by said second certain memory items.

35. In the content-addressable memory of claim 34, and wherein said content-addressable memory further comprises:

an additional plurality of said content-addressable memory modules; and

an additional plurality of said memory match signalling means, each one of said additional plurality of memory match signalling means being connected to said corresponding said match signalling means in each of said content-addressable memory modules of said additional plurality of content-addressable memory modules.