Composite back-etch/lift-off stencil for proximity effect minimization

• US 4,560,435 A
• Filed: 10/01/1984
• Issued: 12/24/1985
• Est. Priority Date: 10/01/1984
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Moore, David F., Brown, Karen H., van der Hoeven, Bernard J. C. Jr.
• Primary Examiner(s): Powell, William A.
• Application Number:
  US06/656,803
• Time in Patent Office: 449 Days
• Field of Search: 156/643, 156/646, 156/652, 156/656, 156/659.1, 156/661.1, 156/904, 29/591, 204/192 EC, 204/192 E, 427/38, 427/39, 427/88-90, 430/313, 430/317, 430/318, 430/314, 357/65, 357/67, 357/68, 357/71, 357/5
• US Class Current: 216/40
• CPC Class Codes: H01L 21/0272 for lift-off processes
• CPC Class Codes: H10N 60/0912 of Josephson-effect devices
• CPC Class Codes: Y10S 438/951 Lift-off
• CPC Class Codes: Y10S 505/82 And etching

Abstract

This composite back-etch/lift-off stencil method avoids the uncontrolled changes in the properties of contacts in small devices caused by the close proximity of the lift-off resist stencil to the contact area during the precleaning, surface preparation and metal deposition processes. This method limits the area of the wafer exposed to back-etching and thus restores the freedom of choice of contact metallurgy. Back-etching is only applied in the areas of the wafer near to the contact holes; lift-off techniques are used for the rest of the integrated circuit.

Claims

1. A method for making integrated circuits having critical wafer areas which are susceptible to proximity effect degradation at critical areas --characterized by--

(a) patterning a lift-off resist stencil factor with windows including contact dimensions and extension dimensions extending beyond the contact dimensions in the critical areas with respect to proximity effects;

(b) depositing contact metal using the windows as a pattern, covering both contact dimensions and extension dimensions;

(c) patterning a back-etch resist stencil factor over selected portions of said contact metal, providing protection to the underlying layers within the contact dimensions but exposing contact metal within the extension dimensions;

(d) back etching to the selected pattern of metallization by removing contact metal from the extension dimensions; and

(e) removing said lift-off resist stencil factor and said back-etch resist stencil factor.

2. A method for making integrated circuits having critical wafer areas with respect to proximity effects, which areas require protection from process-related degradation --characterized by --

(a) patterning a lift-off resist stencil factor over the wafer omitting the critical areas with respect to proximity effects;

(b) patterning a combination contact metal stencil factor generally coextensive to the critical areas, using the lift-off resist stencil factor as a pattern, providing coverage with contact metal material in the critical areas not only where desired as a contact metallization, but with excess coverage extending to the boundary of said lift-off resist stencil factor, whereby a composite contact metal/lift-off stencil is completed;

(c) patterning a back-etch resist stencil over selected portions of said contact metal stencil factor extending less than the entire distance to said lift-off resist stencil factor, to define a desired metal contact configuration;

(d) back-etching said contact metal stencil factor to the selected configuration of contact metal; and

(e) removing the lift-off resist stencil factor;

whereby the contact metal remains in the selected configuration and the critical area remains free of lift-off stencil factor and any resulting proximity effects.