Low power oscillator circuit

• US 4,560,954 A
• Filed: 12/24/1981
• Issued: 12/24/1985
• Est. Priority Date: 12/24/1981
• Status: Expired due to Fees

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Leach, Jerald G.
• Primary Examiner(s): LaRoche, Eugene R.
• Assistant Examiner(s): Pascal, Robert J.
• Application Number:
  US06/334,487
• Time in Patent Office: 1,461 Days
• Field of Search: 331/45, 331/50, 331/55, 331/56, 331/57, 331/104, 331/108 A, 331/108 B, 331/108 C, 331/111, 331/113 R, 331/143, 331/144, 331/DIG. 3, 307/445, 307/448, 307/480, 307/481, 307/482
• US Class Current: 331/108.00B
• CPC Class Codes: H03K 3/014 Modifications of generator to ensure starting of oscillations
• CPC Class Codes: H03K 3/03 Astable circuits
• CPC Class Codes: H03K 3/354 Astable circuits
• CPC Class Codes: Y10S 331/03 Logic gate active element oscillator

Abstract

A low power oscillator circuit including a latch connected to two loops. Each loop includes dynamic inverters and static inverters connected in cascade. The loops are connected to the latch such that the output of the final stage is an input to the latch. An initialization circuit is included on one loop to initiate oscillation. Storage capacitors are included in the loops to provide an oscillator output voltage that is greater than the oscillator power supply voltage.

Claims

1. A digital oscillator, comprising:

first and second oscillator loops, each including a logical combination gate within the loop, a plurality of low power inverters connected in cascade from a first low power inverter to a last low power inverter, and a feedback capacitor connected from an output of a second inverter of said plurality of the low power inverter inverters to an input of the first low power inverter the output of a last member of said plurality of low power inverters being connected to a first input of said logical combination gate;

first and second connection means where the first connection means being for connecting the output of the logical combination gate of the first oscillator loop to the input of the first low power inverter means of the first oscillator loop and to a second input of the logical combination gate of the second oscillator loop and wherein the second connection means being for connecting the output of the logical combination gate of the second oscillator loop to the input of the first low power inverter means of the second oscillator loop and to a second input of the logical combination gate of the first oscillator loop such that the logical combination gates of said first and second oscillator loops being connected together to form a bistable multivibrator to produce alternate pulses of oscillator output signals at respective outputs of said logical combination gates;

at least one of said inverters in each of said oscillator loops including;

a precharge/discharge node;

means for selectively preventing current flow through said precharge/discharge node;

means for establishing a precharge voltage on said precharge/discharge node during a time when said precharge/discharge node has no current flow, and

means for selectively allowing the current flow through said precharge/discharge node for discharging said precharge voltage to produce an inverter output; and

each of said low power inverters comprises;

a first, second and third MOSFET device connected in series from the first to third MOSFET devices in a first circuit,

the control elements of a first and second of said MOSFET devices being connected to receive respective first and second out of phase clock pulses;

a capacitor connected between the control element of the second MOSFET device and a node at an interconnection between said first and second MOSFET devices said node being said precharge/discharge node;

said third MOSFET device having its control element connected to receive an input signal;

at least three MOSFET devices connected in series in a second circuit;

the control element of an outside one of said at least three MOSFET devices being connected to said precharge/discharge node;

the control element of the other outside one of said at least three MOSFET devices being connected to receive the input signal;

the control element of at least one central MOSFET device of said at least three MOSFET devices being connected to receive the clock signal connected to said control element of said MOSFET in said first series circuit to which said capacitor is connected, an inverter output being developed at an interconnection between said at least one central MOSFET device and the other outside one of said at least three MOSFET devices.

2. The oscillator circuit of claim 1 further comprising:

timing signal means connected to the outputs of the logical combination gates of the first and second oscillator loops for generating timing signals.