Implantable cardiac pacer with discontinuous microprocessor programmable antitachycardia mechanisms and patient data telemetry

• US 4,561,442 A
• Filed: 10/17/1983
• Issued: 12/31/1985
• Est. Priority Date: 10/17/1983
• Status: Expired due to Term

• Current Assignee: Pacesetter Incorporated (Abbott Laboratories Incorporated)
• Original Assignee: Cordis Corporation (Cardinal Health, Inc.)
• Inventors: Vollmann, William, Mumford, Van E.
• Primary Examiner(s): Kamm, William E.
• Application Number:
  US06/542,889
• Time in Patent Office: 806 Days
• Field of Search: 128/419 PG
• US Class Current: 607/15
• CPC Class Codes: A61N 1/3621 for treating or preventing abnormally high heart rate
• CPC Class Codes: A61N 1/37211 Means for communicating with stimulators
• CPC Class Codes: A61N 1/37264 Changing the program; Upgrading firmware

Abstract

A multi-programmable ROM-less cardiac pacer employs an intermittent microprocessor turned ON and OFF by a pacer timer clockwise independent of the processor to time intervals preset by the processor. Sensed activity and external communications restart the processor with an interrupt request. Five antitachycardia mechanisms are externally programmable: programmed burst, burst rate scanning, automatic overdrive, programmed critically timed and critically timed scanning. In scanning mechanisms, the interval changes progressively until the tachycardia is terminated by a successful interval which is stored. Runaway protection is executed in the software. For telemetry, the pacer collects the following monitored pacing data over a programmable period of time: percent pacing, average rate, maximum rate, number of tachycardia episodes and maximum tachycardia duration.

Claims

1. An implantable computer-based cardiac pacer comprising

at least one pacer terminal,

output means for issuing an output via said terminal in response to an output command,

a computer including including digital storage with stored program means for defining a series of instructions and processing means for fetching and executing said instructions,

said stored program means including means defining a main pacing routine for issuing an output command in accordance with internal timing logic,

clock means connected to said processing means for running said computer means,

presettable timer means clockwise independent of said computer for receiving a preset number from said computer and for producing a zero output at the end of the time period corresponding to said present number,

said stored program means further including means for loading said timer means with a preset number and then issuing a halt command,

clock control means responsive to said halt command for disabling the clock means output for stopping said computer and responsive to either the zero output of said timer means or to a signal originating externally of said pacer for enabling said clock means to restart said computer,

said timer means including a presettable down counter producing said zero output and an up counter and means for presetting and enabling said down counter substantially simultaneously with resetting said counter, and

parallel bus means for connecting the present input of said down counter and a set of parallel outputs of said up counter to said computer to transfer parallel binary numbers from said computer to said down counter and from said up counter to said computer on command.

2. An implantable electronic biomedical device for monitoring bio-electrical activity, comprising

a terminal for connection to electrically active tissue,

a CPU for executing stored instructions,

a CPU clock disabled by a halt command from said CPU,

a timer clockwise independent of said CPU,

means arising from instruction execution by said CPU for presetting said timer to a variable time interval and issuing a half command,

means responsive to the timing out of said timer for restarting said CPU clock,

means response to electrical activity at said terminal for restarting said CPU clock and issuing an interrupt request for said CPU,

means for keeping track of the elapsed time while said CPU clock is OFF, and

means responsive to the timing out of said timer for disabling said interrupt request means.

3. The device of claim 2, further comprising

means responsive to the timing out of said timer for disabling said interrupt request means.

4. The device of claim 2, further comprising

means responsive to an externally generated communication for restarting said CPU clock and issuing an interrupt request to said CPU.

5. The device of claim 4, further comprising means for giving interrupt priority to said communication.

6. The stimulator of claim 5, further comprising

means responsive to an externally generated communication for restarting said CPU lock and issuing an interrupt request to said CPU.

7. The stimulator of claim 5, further comprising

means for giving interrupt priority to said communication.

8. An implantable tissue stimulator, comprising

a terminal for connection to electrically active tissue,

a CPU for executing stored instructions.

a CPU clock disabled by a halt command from said CPU,

a timer clockwise independent of said CPU,

means arising from instruction execution by said CPU for presetting said timer to a variable timer interval and issuing a halt command,

means responsive to the timing out of said timer for restarting said CPU clock,

means arising from instruction execution for causing said CPU to issue an output command according to a predetermined schedule,

means responsive to a CPU output command for applying electrical stimulation via said terminal,

means for keeping track of the elapsed time while said CPU clock is OFF,

means responsive to spontaneous electrical activity at said terminal for restarting said CPU clock and issuing an interrupt request to said CPU, and

means responsive to the timing out of said timer for disabling said interrupt request means.

9. The stimulator of claim 8, further comprising

means responsive to spontaneous electrical activity at said terminal for restarting said CPU clock and issuing an interrupt request to said CPU.

10. The stimulator of claim 16, further comprising

means responsive to the timing out of said timer for disabling said interrupt request means.

11. An implantable cardiac pacer, comprising

an electrical terminal for connection to cardiac tissue,

sensing means connected to said terminal for producing a sense output indicative of cardiac activity,

a CPU for executing stored instructions,

a CPU clock disabled by a halt command,

a presettable pacer timer clockwise independent of said CPU having a preset input intercommunicated with said CPU,

means arising from instruction execution by said CPU for loading a number indicative of a variable time interval via the present input to said pacer timer and for issuing a halt command to stop said CPU clock,

means for determining the correct number to load into said pacer timer to time respective different portions of a predetermined pacer cycle,

means defining corresponding tasks to be performed by the CPU upon restarting of said CPU clock, depending upon the point within the pacer cycle at which said CPU clock is restarted,

means responsive to the timing out of said pacer timer for re-enabling said CPU clock,

means responsive to said sense output for re-enabling said CPU clock and issuing an interrupt request to said CPU,

means for keeping track of the elapsed time while said CPU clock is OFF;

output means for applying an electrical stimulation pulse via said terminal in response to an output command from said CPU,

means arising from instruction execution by said CPU for disabling said sensing means, issuing an output command and loading a number into the timer via the preset input equivalent to at least a portion of the remainder of the refractory period and issuing a halt command to stop the CPU clock,

means arising from instruction execution by said CPU upon the restarting of the CPU clock after timing out of said pacer timer for terminating the refractory period by enabling said sensing means, loading a number equivalent to the remainder of a minimum rate interval into said pacer time via the preset input and issuing a half command to stop the CPU clock,

real time clock register accessible to said CPU, and

means for incrementing said real time clock register while the CPU is running and for adding to said real time clock register said elapsed time after the CPU clock is restarted.

12. The cardiac pacer of claim 11, wherein said logic means further includes

means responsive to restarting of the CPU clock by the occurrence of either a sensed output or the timing out of the minimum rate interval by the pacer timer in an alert period for resetting the pacer cycle timing.

13. An implantable cardiac pacer, comprising

an electrical terminal for connection to cardiac tissue,

sensing means connected to said terminal for producing a sense output indicative of cardiac activity,

a CPU for executing stored instructions,

a CPU clock disabled by a halt command,

a presettable pacer timer clockwise independent of said CPU having a preset enable input intercommunicated with said CPU,

means arising from instruction execution by said CPU for loading a number indicative of a variable time interval via the preset input to said pacer timer and for issuing a halt command to stop said CPU clock,

means for determining the correct number to load into said pacer timer to time respective different portions of a predetermined pacer cycle,

means defining corresponding tasks to be performed by the CPU upon restarting of said CPU clock, depending upon the point within the pacer cycle at which said CPU clock is restarted,

means responsive to the timing out of said pacer timer for re-enabling said CPU clock,

means responsive to said sense output for re-enabling said CPU clock and issuing an interrupt request to said CPU,

means for keeping track of the elapsed time while said CPU clock is OFF;

output means for applying an electrical stimulation pulse via said terminal in response to an output command from said CPU,

means arising from instruction execution by said CPU for disabling said sensing means, issuing an output command and loading a number into the timer via the preset input equivalent to at least a portion of the remainder of the refractory period and issuing a halt command to stop the CPU clock,

means arising from instruction execution by said CPU upon the restarting of the CPU clock after timing out of said pacer timer for terminating the refractory period by enabling said sending means, loading a number equivalent to the remainder of a minimum rate interval into said pacer timer via the preset input and issuing a halt command to stop the CPU clock,

charge dump means responsive to commands from said CPU for removing residual charge remaining on the terminal after a stimulation output,

means arising from instruction execution from issuing a begin charge dump command by said CPU after a stimulation output command, loading a preset number into said pacer timer equivalent to the remainder of a charge dump period and issuing a halt command to stop the CPU clock,

means arising from instruction execution following the re-enabling of the CPU clock at the end of the charge dump period for terminating charge dumping by issuing an end charge dump command, loading a new preset number into said pacer timer equivalent to the remainder of the refractory period, followed by a halt command to stop the CPU clock.