Universal ultra-precision PSK modulator with time multiplexed modes of varying modulation types

• US 4,562,415 A
• Filed: 06/22/1984
• Issued: 12/31/1985
• Est. Priority Date: 06/22/1984
• Status: Expired due to Term

• Current Assignee: General Dynamics Decision Systems, Inc. (General Dynamics Corporation)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: McBiles, Carol D.
• Primary Examiner(s): LaRoche, Eugene R.
• Assistant Examiner(s): MIS, DAVID C
• Application Number:
  US06/623,688
• Time in Patent Office: 557 Days
• Field of Search: 332/9 R, 332/16 R, 332/19, 332/21, 332/23 R, 375/52, 375/53, 375/54, 375/55, 375/56, 375/57, 375/67
• US Class Current: 332/104
• CPC Class Codes: H04L 27/2035 using a single or unspecified number of carriers

Abstract

An apparatus and method is disclosed which provides PSK modulation utilizing a single balance mixer. This apparatus allows the selection of any type of PSK modulation for each burst of data transmitted through the apparatus. This apparatus further provides a signal having little or no amplitude modulation and reduces the spectrum occupancy to reduce cross channel interference.

Claims

1. A modulator having a carrier signal input, a data input, a mode select input, a clock input and an output, said modulator comprising:

control means for controlling the type of modulation of said modulator, said control means having a first input, a second input, a third input, a fourth input and an output, said first input being coupled to said carrier signal input of said modulator, said second input being coupled to said data input of said modulator, said third input being coupled to said mode select input of said modulator and said fourth input being coupled to said clock input of said modulator; and

a mixer having a first input, a second input and an output, said first input being coupled to said carrier signal input of said modulator, said second input being coupled to said output of said control means and said output being coupled to said output of said modulator.

2. The modulator of claim 1 wherein said first input of said mixer is coupled to said carrier signal input of said modulator through carrier modifying means for modifying a carrier signal input to said modulator, said carrier modifying means having an input and an output, said input being coupled to said input of said modulator and said output being coupled to said first input of said mixer.

3. The modulator of claim 2 wherein said carrier modifying means comprises:

a first divider having an input and an output said input being coupled to said input of said carrier modifiying means; and

a first filter having an input and an output, said input being coupled to said output of said first divider and said output being coupled to said first input of said mixer.

4. The modulator of claim 3 wherein said first filter comprises a bandpass filter having an input and an output, said input being coupled to said input of said first filter and said output being coupled to said output of said first filter.

5. The modulator of claim 1 wherein said output of said mixer is coupled to said output of said modulator through a second filter having an input and an output, said input being coupled to said output of said mixer and said output being coupled to said output of said modulator.

6. The modulator of claim 5 wherein said second filter comprises a bandpass filter having an input and an output, said input being coupled to said input of said second filter and said output being coupled to said output of said second filter.

7. The modulator of claim 5 wherein said first input of said mixer is coupled to said carrier signal input of said modulator through carrier modifying means for modifying a carrier signal input to said modulator, said carrier modifying means having an input and an output, said input being coupled to said carrier signal input of said modulator and said output being coupled to said first input of said mixer.

8. The modulator of claim 7 wherein said carrier modifying means comprises;

a first divider having an input and an output said input being coupled to said input of said carrier modifiying means; and

a first filter having an input and an output, said input being coupled to said output of said first divider and said output being coupled to said first input of said mixer.

9. The modulator of claim 8 wherein said first filter comprises a bandpass filter having an input and an output, said input being coupled to said input of said first filter and said output being coupled to said output of said first filter.

10. The modulator of claim 9 wherein said second filter comprises a bandpass filter having an input and an output, said input being coupled to said input of said second filter and said output being coupled to said output of said second filter.

11. A method of producing a modulated signal comprising the steps of:

providing a carrier signal, a data signal and a mode selection signal;

selecting a desired phase using said data signal and said mode selection signal;

comparing said desired phase to a phase of said carrier signal;

adjusting said phase of said carrier signal to said desired phase producing an adjusted carrier signal;

modifying said carrier signal producing a modified carrier signal;

mixing said adjusted carrier signal with said modified carrier signal producing a mixed signal; and

filtering said mixed signal producing said modulated signal.

12. A modulator having a carrier signal input, a data input, a mode select input, a clock input and an output, said modulator comprising:

a first divider having an input and an output, said input being coupled to said carrier signal input of said modulator;

a first filter having an input and an output, said input being coupled to said output of said first divider;

a mixer having a first input, a second input and an output, said first input being coupled to said output of said first filter;

a second divider having a first input, a second input, a first output and a second output, said first input being coupled to said carrier signal input of said modulator and said second output being coupled to said second input of said mixer;

control logic means for controlling the phase shift of a data signal, said control means having a first input, a second input, a third input, a fourth input, and an output, said first input being coupled to said data input of said modulator, said second input being coupled to said mode select input of said modulator, said third input being coupled to said clock input of said modulator, said fourth input being coupled to said first output of said second divider and said output being coupled to said second input of said second divider;

a second filter having an input and an output, said input being coupled to said output of said mixer and said output being coupled to said output of said modulator.

13. The modulator of claim 12 wherein said first filter comprises a bandpass filter having an input and an output said input being coupled to said input of said first filter and said output being coupled to said output of said first filter.

14. The modulator of claim 13 wherein said second filter comprises a bandpass filter having an input and an output, said input being coupled to said input of said second filter and said output being coupled to said output of said second filter.

15. The modulator of claim 14 wherein said first divider comprises a divide-by-M wherein M is defined by 2ⁿ and where n is an integer greater than or equal to 1.

16. A modulator having a carrier input, a data input, a data clock input, a mode select input and an output, said modulator comprising:

a shift register having a data input, a clock input and an output, said input being coupled to said data input of said modulator and said clock input being coupled to said data clock input of said modulator;

a programmable read only memory having a first address input, a second address input, a phase magnitude output and a phase sign output, said first address input being coupled to said mode select input of said modulator and said second address input being coupled to said output of said shift register;

a bit/symbol clock generator having an input, a clock input, a carrier input, a load output and a clock output, said input being coupled to said mode select input of said modulator, said clock input being coupled to said data clock input of said modulator and said carrier input being coupled to said carrier input of said modulator;

a first logic gate having an input and an output, said input being coupled to said phase magnitude output of said programmable read only memory;

a second logic gate having first and second inputs and an output, said first input being coupled to said output of said first logic gate and said second input being coupled to said clock output of said bit/symbol clock generator;

a third logic gate having an input and an output, said input being coupled to said output of said second logic gate;

a fourth logic gate having first and second inputs and an output, said first input being coupled to said output of said first logic gate and said second input being coupled to said output of said third logic gate;

a fifth logic gate having first and second inputs and an output, said second input being coupled to said output of said fourth logic gate;

a sixth logic gate having first and second inputs and an output, said second input being coupled to said phase sign output of said programmable read only memory and said output being coupled to said first input of said fifth logic gate;

a switch having first and second positions and an output, said first position being adapted to couple said output to an external spectrum control signal, said second position being adapted to couple said output to a ground and said output being coupled to said first input of said sixth logic gate;

a phase magnitude counter having an input, a load input, a load clock input, a clock input and an output, said input being coupled to said phase magnitude output of said programmable read only memory, said load input being coupled to said load output of said bit/symbol clock generator and said load clock input being coupled to said clock output of said bit/symbol clock generator;

a seventh logic gate having an input and an output, said input being coupled to said output of said phase magnitude counter;

a phase rate counter having a select input, an enable input, a clock input and an output, said select input being coupled to receive a bit/symbol selection signal, said enable input being coupled to said output of said seventh logic gate, said clock input being coupled to said carrier input of said modulator and said output being coupled to said clock input of said phase magnitude counter;

a presettable counter having an enable input, a clock input, a data input and first and second outputs, said enable input being coupled to said output of said phase rate counter and said clock input being coupled to said carrier input of said modulator;

a full adder having first, second and third inputs and an output, said first input being coupled to ground, said second input being coupled to said output of said fifth logic gate, said third input being coupled to said first output of said presettable counter and said output being coupled to said data input of said presettable counter;

a gated amplifier having an input, a control input and an output, said input being coupled to said second output of said presettable counter and said control input being coupled to receive a carrier control signal;

a divider having an input and an output, said input being coupled to said carrier input of said modulator;

a first bandpass amplifier having an input and an output, said input being coupled to said output of said divider;

a balanced mixer having first and second inputs and an output, said first input being coupled to said output of said first bandpass amplifier and said second input being coupled to said output of said gated amplifier; and

a second bandpass amplifier having an input and an output, said input being coupled to said output of said balanced mixer and said output being coupled to said output of said modulator.

17. The modulator of claim 16 wherein said first, second and fourth logic gates comprise AND gates.

18. The modulator of claim 17 wherein said third logic gate comprises a flip flop coupled to operate as a divide-by-two.

19. The modulator of claim 18 wherein said fifth and sixth logic gates comprise exclusive-OR gates.

20. The modulator of claim 19 wherein said seventh logic gate comprises an OR gate.