Data communications system to system adapter

• US 4,562,533 A
• Filed: 08/20/1984
• Issued: 12/31/1985
• Est. Priority Date: 12/03/1981
• Status: Expired due to Term

• Current Assignee: NCR Corporation
• Original Assignee: NCR Corporation
• Inventors: Merkes, Dennis B., Hodel, Alfred, Chari, Venu
• Primary Examiner(s): Chan, Eddie P.
• Application Number:
  US06/642,736
• Time in Patent Office: 498 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 709/237
• CPC Class Codes: G06F 13/4213 with asynchronous protocol
• CPC Class Codes: G06F 15/17 using an input/output type connection, e.g. channel, I/O port

Abstract

This invention relates to an adapter for interprocessor communications and the method therefor. An adapter is included in a data processing system which has a plurality of central systems, each of the plurality of central systems having at least one serial channel control processor. The data processing system further has a dynamic channel exchange for providing switching logic thereby permitting each of the plurality of central systems access to a plurality of peripherals coupled to the dynamic channel exchange. The adapter is operatively connected to the dynamic channel exchange for providing communications between any pair of central systems. The adapter comprises a link control module which provides handshake control to perform message bit/byte synchronization and translation. A message protocol module, which is operatively connected to the link control module, controls the transmission of information with a selected one of the plurality of central systems, the control being administered by interfacing with the serial channel control processor in accordance with a defined message protocol. A data buffer provides intermediate storage of information passed between the pair of central systems. A control processor schedules and monitors the information transfer into and out of the data buffer by interfacing with the message protocol module in accordance with the defined message protocol thereby achieving the information transfer between the pair of central systems.

Claims

1. In a data processing system having a plurality of central systems, each of said central systems having

a central memory,

a processor and

at least one serial channel control processor (SCCP), said data processing system further having an adapter for providing for the exchange of data between two of said central systems, said adapter acting as a peripheral of one central system and then as a pheripheral of the other central system, the method of exchanging data between two of said central systems comprising the steps of:

a. executing first I/O instructions from the processor of a first central system when the first central system desires to receive data from a second central system;

b. responsive to said first I/O instructions, establishing by said processor of the first central system in the central memory of said first central system, a first I/O field which includes a check field and a first starting address for storing the data to be received;

c. after establishing the I/O field in the first central memory, issuing first instructions by the first central system processor to the SCCP of said first central system to engage in a first command message sequence with said adapter, said first command message sequence for establishing communications with a second central system, and containing said check field and the address of said first I/O field;

d. transmitting said first command message sequence including said check field and said address of said first I/O field between the SCCP of the first central system and said adapter;

e. responsive to said first command message sequence, said adapter storing said check field and said address of said first I/O field;

f. when data is to be transferred from said second to said first central systems, executing second I/O instructions from the processor of said second central system;

g. responsive to said second I/O instructions, establishing by said processor of said second central system in the central memory of said second central system, a second I/O field which includes said check field and a second starting address in said second central memory for locating the data to be transferred;

h. after establishing the second I/O field in the second central memory, issuing instructions by the second central system processor to the SCCP of said second central system to engage in a second command message sequence with said adapter, said second command message sequence for completing communication with said first central system, and containing said check field and the address of said second I/O field;

i. transmitting said second command message sequence including said check field and said address of said second I/O field between the SCCP of the second central system and said adapter;

j. responsive to said second command message sequence, said adapter storing said check field and said address of said second I/O field;

k. issuing a first service needed message from said adapter to said second central system;

l. responsive to said first service needed message, verifying by the SCCP of said second central system that the check field stored in said adapter is the same as the check field included in said second I/O field from the second I/O field address in the memory of said second central system;

m. responsive to positive verification in step 1, transmitting by the SCCP of said second central system, data from the central memory of said second central system to said adapter;

n. subsequent to the successful completion of step m, issuing a second service needed message from said adapter to said first central system;

o. responsive to said second service needed message, verifying by the SCCP of said first central system that the check field stored in said adapter is the same as the check field included in said first I/O field from the first I/O field address in the memory of said first central system; and

p. responsive to positive verification in step o, transmitting the data received by said adapter in step m from said adapter to the central memory of said first central system.

2. The method of claim 1 wherein step m. comprises:

a". the SCCP of said second central system getting data starting from the second starting address in the central memory of said second central system as included in the second I/O field in the central memory of said second central system, and storing the data in a buffer in said second central system SCCP;

b". the SCCP of said second central system transmitting the data stored in said second central system SCCP to said adapter; and

c". the adapter storing the transmitted data in a buffer in said adapter.

3. The method of claim 2 wherein step p. comprises:

a"'"'"'. the adapter transmitting data stored in said buffer in said adapter to said first central system SCCP;

b"'"'"'. the SCCP of said first central system storing the data transmitted in step a"'"'"' in a buffer in said first central system SCCP; and

c"'"'"'. the SCCP of said first central system effecting the dispositioning of the data stored in step b"'"'"' starting at the first starting address in said first central memory as included in the first I/O field in the central memory of said first central system.

4. The method of claim 1 including, subsequent to transmitting steps d, i, m and p, placing said adapter in an idle state.

5. In a data processing system having a plurality of central systems, each of said central systems having

a central memory,

a processor and

at least one serial channel control processor (SCCP), said data processing system further having an adapter for providing for the exchange of data between two of said central systems, said adapter acting as a peripheral of one central system and then as a peripheral of the other central system, the apparatus for exchanging data between two of said central systems comprising:

a. means in the processor of a first central system for executing first I/O instructions when the first central system desires to receive data from a second central system;

b. means in said processor of the first central system responsive to said first I/O instructions for establishing in the central memory of said first central system, a first I/O field which includes a check field and a first starting address for storing the data to be received;

c. means in the first central system processor for issuing, after establishing the first I/O field in the first central memory, instructions to the SCCP of said first central system to engage in a first command message sequence with said adapter, said first command message sequence for establishing communications with a second central system, and containing said check field and the address of said first I/O field;

d. means for transmitting said first command message sequence including said check field and said address of said first I/O field between the SCCP of the first central system and said adapter;

e. means in said adapter responsive to said first command message sequence for storing said check field and said address of said first I/O field;

f. means in the processor of said second central system for executing second I/O instructions when data is to be transferred from said second to said first central systems;

g. means in said processor of said second central system responsive to said second I/O instructions for establishing in the central memory of said second central system, a second I/O field which includes said check field and a second starting address in said second central memory for locating the data to be transferred;

h. means in the second central system processor for issuing instructions, after establishing the second I/O field in the second central memory, to the SCCP of said second central system to engage in a second command message sequence with said adapter, said second command message sequence for completing communication with said first central system, and containing said check field and the address of said second I/O field;

i. means for transmitting said second command message sequence including said check field and said address of said second I/O field between the SCCP of the second central system and said adapter;

j. means in said adapter responsive to said second command message sequence for storing said check field and said address of said second I/O field;

k. means in said adapter for issuing a first service needed message to said second central system;

l. means in the SCCP of said second central system responsive to said first service needed message for verifying that the check field stored in said adapter is the same as the check field included in said second I/O field from the second I/O field address in the memory of said second central system;

m. means in the SCCP of said second central system responsive to positive verification of the SCCP of said second central system for transmitting, data from the central memory of said second central system to said adapter;

n. means in said adapter for issuing a second service needed message to said first central system subsequent to the successful transmission of data from the central memory of said second central system to said adapter;

o. means in the SCCP of said first central system responsive to said second service needed message for verifying that the check field stored in said adapter is the same as the check field included in said first I/O field from the first I/O field address in the memory of said first central system; and

p. means responsive to said positive verification of the SCCP of said first central system for transmitting to the central memory of said first central system, the data received by said adapter from said second central system.