Schmitt trigger circuit using MOS transistors and having constant threshold voltages

• US 4,563,594 A
• Filed: 07/25/1983
• Issued: 01/07/1986
• Est. Priority Date: 07/30/1982
• Status: Expired due to Term

• Current Assignee: Tokyo Shibaura Denki Kabushiki Kaisha (Toshiba Corporation)
• Original Assignee: Tokyo Shibaura Denki Kabushiki Kaisha (Toshiba Corporation)
• Inventors: Koyama, Mikio
• Primary Examiner(s): Anagnos, Larry N.
• Assistant Examiner(s): HUDSPETH, DAVID R
• Application Number:
  US06/516,762
• Time in Patent Office: 897 Days
• Field of Search: 307/443, 307/451, 307/359, 307/579, 307/585, 307/279, 307/290, 307/603, 307/605
• US Class Current: 327/206
• CPC Class Codes: H03K 3/3565 Bistables with hysteresis, e.g. Schmitt trigger

Abstract

An input CMOS inverter comprises a complementary pair of first and second MOS transistors having their gates connected together to receive an input signal, and a buffer circuit connected between drains of the first and second MOS transistors. The buffer circuit is preferably an analog switch circuit having a complementary pair of third and fourth MOS transistors responsive to the input signal and connected in parallel. In response to a potential variation caused at the drain of one of the first and second transistors, the buffer circuit causes a potential variation at the drain of the other transistor after a delay. There is provided a second MOS inverter having a complementary pair of fifth and sixth MOS transistors with their gates connected to the drains of the first and second transistors, respectively. A feedback circuit is connected to the output of the second inverter to suppress the potential variation at the drains of the first and second transistors. The feedback circuit preferably includes a third inverter and a complementary pair of seventh and eighth MOS transistors connected to the drains of the first and second transistors, respectively, and controlled by the third inverter.

Claims

1. A Schmitt trigger circuit having lower and higher threshold voltages, comprising:

first and second power supply terminals between which an operating voltage is applied;

first MOS inverter means including a complementary channel conductivity pair of first and second MOS transistors each having a drain, a source and a gate, said first and second MOS transistors having their gates connected together to receive an input voltage signal, and their sources connected to said first and second power supply terminals, respectively, and circuit means connected between the drains of said first and second MOS transistors for transmitting a potential variation at the drain of one of said first and second MOS transistors, which potential variation is caused by a voltage variation of said input voltage signal, to the drain of the other transistor after a delay;

second MOS inverter means responsive to said first MOS inverter means; and

feedback circuit means responsive to said second MOS inverter for suppressing the potential variation at the drain of at least one of said first and second MOS transistors of said first MOS inverter means until said input voltage signal becomes lower than said lower threshold voltage or higher than said higher threshold voltage of said Schmitt trigger circuit; and

output means coupled to said feedback circuit means for providing an output voltage signal of said Schmitt trigger circuit.

2. A Schmitt trigger circuit according to claim 1, wherein said second MOS inverter means comprises a complementary channel conductivity pair of third and fourth MOS transistors each having a drain, a source and a gate, and connected with the source-drain paths thereof in series between said first and second power supply terminals, the gates of said third and fourth MOS transistors being connected to the drains of said first and second MOS transistors, respectively.

3. A Schmitt trigger circuit according to claim 2, wherein said third and fourth MOS transistors are complementary to said first and second MOS transistors, respectively, and the sources of said third and fourth MOS transistors are connected to said second and first power supply terminals, respectively.

4. A Schmitt trigger circuit according to claim 2, wherein said third and fourth MOS transistors are complementary to said second and first MOS transistors, respectively, and the sources of said third and fourth MOS transistors are connected to said first and second power supply terminals, respectively.

5. A Schmitt trigger circuit according to claim 1, wherein said circuit means comprises a complementary channel conductivity pair of parallel-connected MOS transistors having their gates connected together to receive the input signal.

6. A Schmitt trigger circuit according to claim 1, wherein said circuit means comprises resistor means.

7. A Schmitt trigger circuit according to claim 1, wherein said feedback circuit means comprises third MOS inverter means connected to said second MOS inverter means, and a complementary channel conductivity pair of third and fourth MOS transistors each having a drain-source path and a gate, said third and fourth MOS transistors being complementary to said second and first MOS transistors, respectively, and having their gates connected together to an output of said third MOS inverter means, and their drain-source paths connected between the drain of said first MOS transistor and said second power supply terminal and between the drain of said second MOS transistor and first power supply terminal, respectively.

8. A Schmitt trigger circuit according to claim 1, wherein said feedback circuit means comprises a complementary pair of third and fourth MOS transistors each having a source-drain path and gate, said third and fourth MOS transistors being complementary to said first and second MOS transistors, respectively, and having their gates connected together to an output of said second MOS inverter means, and their drain-source paths connected between the drain of said first MOS transistor and said second power supply terminal and between the drain of said second MOS transistor and said first power supply terminal, respectively.

9. A Schmitt trigger circuit according to claim 8, wherein said feedback circuit means further comprises a cascade connection of an even number of inverters between the output of said second MOS inverter means and the gates of said third and fourth MOS transistors.

10. A Schmitt trigger circuit according to claim 1, wherein said second MOS inverter means comprises cascade connected inverter pairs each connected to a respective one of the drains of said first and second MOS transistors, and wherein said feedback circuit means is arranged to suppress the potential variations at the drains of said first and second MOS transistors in response to said pair of inverters.

11. A Schmitt trigger circuit according to claim 1, wherein said feedback circuit means comprises a third MOS inverter connected to said second MOS inverter means and a third MOS transistor having a source-drain path and a gate, said third MOS transistor having its source-drain path connected in series with the source-drain path of one of said first and second MOS transistors of the same channel type as said third MOS transistor between said first and second power supply terminals, and its gate connected to an output of said third MOS inverter.

12. A Schmitt trigger circuit comprising:

first and second power supply terminals between which an operating voltage is applied;

first MOS inverter means including a complementary channel conductivity pair of first and second MOS transistors each having a drain, a source and a gate, said first and second MOS transistors having their gates connected together to receive an input voltage signal, and their sources connected to said first and second power supply terminals, respectively, and a complementary channel conductivity pair of third and fourth MOS transistors each having a gate, a source, and a drain, said third and fourth MOS transistors having their source-drain paths connected in parallel between said drains of said first and second MOS transistors and their gates connected together to receive the input voltage signal;

second MOS inverter means having a complementary channel conductivity pair of fifth and sixth MOS transistors each having a drain, a source and a gate, said fifth and sixth MOS transistor having their drains connected together, their sources connected to said second and first power supply terminals respectfully, and their gates connected to the drains of said first and second MOS transistors, respectively;

third MOS inverter means having an input connected to said drains of said fifth and sixth MOS transistors; and

a seventh MOS transistor have a source-drain path and a gate, said seventh MOS transistor having its source-drain path connected in series with one of said first and second MOS transistors of the same channel type between said first and second power supply terminals, and its gate connected to an output of said third MOS inverter means.

13. A Schmitt trigger circuit according to claim 12, further comprising an eighth MOS transistor having a source-drain path and gate, said eighth MOS transistor being complementary to said seventh MOS transistor, and having its source-drain path connected in series with the other of said first and second MOS transistors of the same channel type between said first and second power supply terminals, and its gate connected to the output of said third MOS inverter means.

14. A Schmitt trigger circuit according to claim 12, wherein said fifth and sixth MOS transistors are complementary to said first and second MOS transistors, respectively.

15. A Schmitt trigger circuit according to claim 12, wherein said fifth and sixth MOS transistors are complementary to said second and first MOS transistors, respectively.

16. A Schmitt trigger circuit comprising:

first and second power supply terminals between which an operating voltage is applied;

first MOS inverter means including a complementary channel conductivity pair of first and second MOS transistors each having a drain, a source and a gate, said first and second MOS transistors having their gates connected together to receive an input voltage signal, and their sources connected to said first and second power supply terminals, respectively, and a complementary channel conductivity pair of third and fourth MOS transistors having their source-drain paths connected in parallel between said drains of said first and second MOS transistors and their gates connected together to receive the input voltage signal;

second and third MOS inverter means having their inputs connected to the drains of said first and second MOS transistors, respectively;

fourth and fifth MOS inverter means having their inputs connected to outputs of said second and third MOS inverter means, respectively; and

a complementary channel conductivity pair of fifth and sixth MOS transistors each having a source-drain path and a gate, said fifth transistor having its source-drain path connected in series with one of said first and second MOS transistors of the same channel type between said first and second power supply terminals, and its gate connected to an output of one of said fifth and sixth MOS inverters, and said sixth transistor having its source-drain path connected in series with the other of said first and second MOS transistors of the same channel type between said first and second power supply terminals, and its gate connected to an output of the other of said fifth and sixth MOS inverters.

17. A Schmitt trigger circuit comprising:

first and second power supply terminals between which an operating voltage is applied;

first MOS inverter means including a complementary channel conductivity pair of first and second MOS transistor each having a drain, a source and a gate, said first and second MOS transistors having their gates connected together to receive an input voltage signal, and their sources connected to said first and second power supply terminals respectively, and a complementary channel conductivity pair of third and fourth MOS transistors having their source-drain paths connected in parallel between said drains of said first and second MOS transistors and their gates connected together to receive the input voltage signal;

second MOS inverter means having a complementary channel conductivity pair of fifth and sixth MOS transistors each having a drain, a source and a gate, said fifth and sixth MOS transistors being complementary to said first and second MOS transistors, respectively, and their drains being connected together, their sources connected to said second and first power supply terminals, respectively, and their gates connected to the drains of said first and second transistors, respectively; and

a complementary channel conductivity pair of seventh and eighth MOS transistors each having a source-drain path and a gate, said seventh and eighth MOS transistors having their gates connected to the drains of said fifth and sixth transistors, said seventh transistor having is source-drain path connected between said first and second power supply terminals in series with one of said first and second transistors which is complementary to said seventh transistor, and said eighth transistor having its source-drain path connected between said first and second power supply terminals in series with the other of said first and second transistors, which is complementary to said eighth transistor.