Video processing systems

• US 4,563,703 A
• Filed: 03/16/1983
• Issued: 01/07/1986
• Est. Priority Date: 03/19/1982
• Status: Expired due to Term

• Current Assignee: Quantel Limited (Belden Inc.)
• Original Assignee: Quantel Limited (Belden Inc.)
• Inventors: Taylor, Richard J., Hinson, Neil R., Kellar, Paul R. N.
• Primary Examiner(s): Martin, John C.
• Assistant Examiner(s): Harvey, David E.
• Application Number:
  US06/475,789
• Time in Patent Office: 1,028 Days
• Field of Search: 358/160, 358/180, 358/22, 358/183, 358/138, 358/140, 358/134, 382/44, 382/45, 382/46, 382/47
• US Class Current: 348/580
• CPC Class Codes: G06T 3/4007 based on interpolation, e.g. bilinear interpolation image demosaicing G06T3/4015; edge-driven or edge-based scaling G06T3/403
• CPC Class Codes: H04N 5/222 Studio circuitry; Studio devices; Studio equipment cameras or camera modules comprising electronic image sensors, or control thereof H04N23/00
• CPC Class Codes: H04N 5/2628 Alteration of picture size, shape, position or orientation, e.g. zooming, rotation, rolling, perspective, translation

Abstract

A processing system includes a processor 10 and frame store 11. Both the frame store and processor are under the control of address mechanism 12. The addressing mechanism 12 can generate the desired information from address information which is only provided on some of the store locations and which is only updated over more than one frame period. The mechanism includes spatial and temporal address interpolators to effect this operation.

Claims

1. A video processor for picture manipulation comprising:

input means for providing a sequence of picture point signals representing an input picture;

storage means for receiving picture point signals in a plurality of locations representing spaced picture points on spaced lines of an input picture;

a store for address signals identifying selected locations in said storage means;

said selected locations being less numerous than the picture points of said input picture;

means for reading said address signals at a lower rate than that at which said input picture point signals are provided;

means for interpolating among groups of said address signals to provide a respective address signal for each of the input picture point signals;

means for writing said input picture point signals in the locations represented by the respective address signals, and means for reading the picture point signals from said locations in sequence to provide output picture point signals representing said input picture with a manipulation determined by said address signals.

2. A processor according to claim 1, wherein said store for address signals comprises means for providing different address signals for different pictures separated by more than one picture in a sequence of input pictures and said interpolating means comprises means for interpolating address signals for input picture signals occurring in successive pictures.

3. A video processing system comprising:

a frame store;

input means for receiving sequences of picture point signals defining successive pictures;

address means for determining selected addresses in said frame store for picture point signals separated by more than one picture point;

said address means being operative to provide said selected addresses for pictures separated by more than one picture;

address interpolation means for interpolating picture point addresses not determined by said address means in successive pictures including said separated pictures and including intermediate pictures, and means for writing picture point signals in a predetermined order into said frame store means.

4. A system as in claim 3, wherein said address determining means includes a memory for retaining at least one sequence of addresses.

5. A system as in claim 4, wherein said memory comprises a movable recording medium containing only said selected frame store addresses for said separated pictures.

6. A system as in claim 4, including generator means to determine desired sequence of addresses prior to their receipt by said memory.

7. A system as in claim 3, wherein said address interpolation means includes:

a spatial address interpolator for making available interpolated picture point addresses in two separated pictures; and

a temporal address interpolator responsive to the spatial address interpolator for interpolating picture point addresses in pictures intermediate said two separated pictures.

8. A system as in claim 7, wherein said spatial address interpolator includes a processor for providing interpolating coefficients dependent on the spatial relationship of the respective picture points.

9. A system as in claim 8, wherein said temporal address interpolator includes a processor for providing interpolation coefficients dependent on the time separation of the respective pictures.

10. A method of providing addresses for a frame store processing system comprising the steps of:

providing only selected ones of the desired frame store addresses required to be addressed, and updating the selected ones of the desired address at a rate slower than a normal picture rate;

calculating all the desired addresses to be accessed by interpolating from the selected addresses in spatial and temporal modes so that all the addresses to be accessed are available updated at said normal rate.

11. A video processor for picture manipulation comprising:

input means for providing a sequence of picture point signals representing an input picture;

first storage means for receiving picture point signals in a plurality of locations representing picture points on lines of an input picture;

means including second storage means for predetermined address signals identifying selected locations in said first storage means for said picture point signals;

means for reading from said second storage means address signals concommitantly with the provision of said input picture point signals by said input means;

means for writing said input picture point signals in locations of said first storage means determined by respective address signals;

and means for reading the picture point signals from said locations of said first storage means in sequence to provide output picture point signals representing said input picture with a manipulation determined by said address signals.

12. A video processor according to claim 11, wherein said second storage means is arranged to store address signals identifying selected locations in said first storage means, which are less numerous than the picture points on said input picture, and means are provided for interpolating among said address signals to provide address signals for each of said input picture points.