Multiprocessor computer system

• US 4,564,900 A
• Filed: 02/10/1984
• Issued: 01/14/1986
• Est. Priority Date: 09/18/1981
• Status: Expired due to Term

• Current Assignee: Christian Rovsing A/S AF 1984 A Newly Formed Danish Company, Federspiel Herman Gothersgade, Hassel Helge Bergensgade
• Original Assignee: Christian Rovsing A/S
• Inventors: Smitt, Asbjorn
• Primary Examiner(s): Thomas, James D.
• Assistant Examiner(s): Eng, David Y.
• Application Number:
  US06/579,435
• Time in Patent Office: 704 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 371/9, 371/11
• US Class Current: 709/212
• CPC Class Codes: G06F 11/1443 Transmit or communication errors
• CPC Class Codes: G06F 11/2005 using redundant communication controllers
• CPC Class Codes: G06F 11/2007 using redundant communication media
• CPC Class Codes: G06F 11/2017 where memory access, memory control or I/O control functionality is redundant redundant communication control functionality G06F11/2005; redundant storage control functionality G06F11/2089
• CPC Class Codes: G06F 11/2035 without idle spare hardware
• CPC Class Codes: G06F 13/36 for access to common bus or bus system
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 15/17343 wherein the interconnection is dynamically configurable, e.g. having loosely coupled nearest neighbor architecture reconfigurable processors arrays G06F15/7867
• CPC Class Codes: G06F 15/177 Initialisation or configuration control processor initialisation G06F9/4405

Abstract

A multiprocessor computer system wherein memory buses of separate central processing unit systems are interfaced to an intermemory communication network for transfer of data between memories of said separate central processing unit systems.

The intermemory communication network includes a plurality of preferably passive intermemory communication links being tapped for connection to link adapters interfacing a number of central processing unit systems to each intermemory communication link. The number of central processing unit systems may be different for different intermemory communication links.

The memory buses are configurated to allow for direct data transfer between any memory fraction of a common memory shared by at least two central processing unit systems without interfering with the central processing units such that the data transfer is controlled by direct memory access control means.

The multiprocessor computer system includes separate configuration controllers being effective to reconfigurate the overall system in the event of failure. The reconfiguration comprises switching of fractions of memory between the memory buses of at least two central processing unit systems. At least one of the memory fractions is directly addressable by a respective peripheral processor. Also, one of the peripheral processors backs up the others to obtain N+1 redundancy.

Claims

1. A multiprocessing computer system comprising:

(A) a plurality of central processing systems, each system including

(a) at least one central processing unit for processing data in response to instructions and having the capability to produce address source information,

(b) memory means for storing data,

(c) bus means for transferring data between said at least one central processing unit and said memory means,

(d) intermemory link adaptor means connected to said bus means for transporting data externally of said central processing system; and

(e) DMA means associated with said intermemory link adaptor means for producing address source information and for controlling transfers of data via said intermemory link adaptor means and said bus means to and from said memory means without intervention by said at least one central processor unit,

(B) at least a portion of said memory means defining a common memory having separate port means for connecting via respective bus means at least two of said plurality of central processing systems, said separate port means causing said common memory to be shared by the two central processing systems;

(C) at least part of said common memory being compartmentalized and divided into a number of separate memory compartments wherein each of said memory compartments is coupled to a respective data transfer port and to said respective bus means of at least two of said plurality of central processing systems;

(D) at least one peripheral device controller means associated with at least one of said plurality of central processing systems and being adapted for connection with a peripheral device, each said peripheral device controller means being connected to a preselected memory compartment of said common memory via the data transfer port associated with said preselected memory compartment, said peripheral device controller means having means for producing and means for responding to address source information and means for controlling the transfer data between said peripheral device and the preselected memory compartment of said common memory;

(E) an intermemory communication network comprising a plurality of intermemory link means for connection with said intermemory link adaptor means of said plurality of central processing systems and for transferring data among said memory means of respective ones of said plurality of central processing systems; and

(F) DMA interface controller means connected to said intermemory communication network via said intermemory link adaptor means, said DMA interface controller means for controlling access to said memory of each of said plurality of central processing systems via said DMA means, said DMA interface controller means multiplexing transfers of data over said intermemory communication network, said DMA interface controller means being further operative to effect logical connection of at least two intermemory link adaptor means of respective ones of said central processing systems to said intermemory communication network in response to said address source information and to multiplex transfers of data among said memory means of the respective central processing systems over said intermemory communication network without intervention by said associated central processing unit.

2. The multiprocessing computer system as recited in claim 1, wherein at least two of said bus means do not interface with each other but do interface with another bus means via said intermemory communication network.

3. The multiprocessing computer system as recited in claim 1, wherein at least two of said plurality of central processing systems are connected in parallel with respect to said intermemory link adaptor means.

4. The multiprocessing computer system as recited in claim 1, wherein said plurality of central processing means are connected in a series array with respect to said intermemory link adaptor means.

5. The multiprocessing computer system as recited in claim 1, wherein at least one of said central processing systems includes at least two independently operating central processing units.

6. The multiprocessing computer system as recited in claim 1, wherein said intermemory link adaptor means includes arbitration means for operatively connecting said link adaptor means to an intermemory link to control contention and transfers of data over said intermemory communication network.

7. The multiprocessing computer system as recited in claim 1, wherein the compartmentalized common memory includes a spare memory compartment, and wherein said multiprocessing computer system further comprises:

at least one spare peripheral device controller means for connection with said bus means of said at least one of said central processing systems through said spare memory compartment;

configuration control processor means for monitoring failures in a group of components including said memory compartments and said peripheral device controllers and for generating reconfiguration information in response to a failure therein; and

configuration adaptor means responsive to said reconfiguration information for substituting said spare peripheral device controller means and the respective spare memory compartment in place of a failed peripheral device controller memory and its memory compartment.

8. The multiprocessing computer system as recited in claim 7, wherein said intermemory link adaptor means comprises enabling/disabling means connected to a respective configuration adaptor means, said configuration adaptor means being effective to disconnect the bus means from said intermemory link adaptor means.

9. The multiprocessing computer system as recited in claim 7, further comprising bus separators wherein at least part of said memory means is addressable by said address source information and is connected to said bus means of said at least one central processing system via separate bus separators, each part of said memory means being enabled or disabled by said configuration adaptor means.

10. The multiprocessing computer system as recited in claim 9, wherein the respective parts of said memory means are individually powered by at least two power supplies.

11. The multiprocessing computer system as recited in claim 7, wherein said configuration adaptor means includes a configuration bus for transferring said configuration information which is electrically isolated from said configuration adaptor means.

12. The multiprocessing computer system as recited in claim 7, wherein said configuration adaptor means further comprises input means for receiving information from detector means distributed throughout said multiprocessing computer system for monitoring operating conditions and detecting faults in said multiprocessing computer system, said input means being accessible via said configuration adaptor means and via said configuration bus by a configuration control processor for monitoring operating conditions and faults and for generating reconfiguration information in response thereto.

13. The multiprocessing computer system as recited in claim 12, wherein the conditions being monitored include voltage, current, and temperature in at least one portion of said multiprocessing computer system.

14. The multiprocessing computer system as recited in claim 7, further comprising a back-up controller connected to said configuration bus, said configuration bus having redundant paths separately connected to said configuration control processor means and to said back-up controller, and switching means responsive to a malfunction of said configuration control processor means for alternately enabling one of said paths while disabling the other of said paths.

15. The multiprocessing computer system as recited in claim 14, wherein said back-up controller comprises:

a plurality of manually setable switches, the positions thereof defining a predetermined configuration of said multiprocessing computer system representative of said configuration information, and

scanning means for scanning the positions of said switches and to transfer corresponding configuration information to a respective configuration bus through an enabled path thereof.

16. The multiprocessing computer system as recited in claim 14, wherein said back-up controller comprises a manually setable switch overriding said switching means.

17. The multiprocessing computer system as recited in claim 7, wherein a number of said peripheral device controller means is arranged to address only one respective compartment of the compartmentalized common memory means, the respective memory compartments being separately and operatively connected to said bus means of said at least one central processing system, said multiprocessor computer system further comprising:

a plurality of switchover modules, the number of switchover modules being one less than the said number of peripheral device controller means, and each of said plurality of switchover modules being controlled by a respective one of said configuration adaptor means,

a plurality of peripheral devices connected via respective switchover modules to said number of peripheral device controller means but one of said peripheral devices when said switchover modules are arranged in a first position, and

a spare peripheral device controller means connected to said one of said peripheral devices via a respective switchover module when said module is arranged in a second position.

18. In a multiprocessing computer system, a central processing system comprising:

a plurality of central processing units processing data in response to instructions and having means for producing address source information,

memory means for storing data,

a plurality of address sourcing devices other than said plurality of central processing units producing address source information for transferring and storing data,

first bus means associated with said plurality of central processing units and with a first portion of said memory means for transferring data among said plurality of central processing units and said memory means along a first memory path,

second bus means for connecting said plurality of address sourcing devices along a second memory path to said first portion of said memory means, and for connecting said at least one central processing unit and at least one of said plurality of said address sourcing devices along a third common extension path to a second portion of said memory means, said first and second memory paths enabling said at least one central processing unit and said at least one address sourcing devices to access said first portion of said memory means without contention, and being effective to reduce contention among each other when accessing said second portion of said memory means,

intermemory link adaptor means connected to said second bus means for transferring data externally of said central processing system to and from the memory means of selected ones of said plurality of central processing systems, and

DMA interface controller means cooperating with the producer of said address source information for controlling external transfers of data via said intermemory link adaptor means, so as to provide decreased contention between respective memory means in said central processing system and in the external central processing system.

19. In the multiprocessing computer system recited in claim 18, including a plurality of central processing systems, an intermemory communication network to which said plurality of central processing systems connect for transferring data among their respective memory means via respective intermemory link adaptor means, at least two specified central processing systems of said plurality of central processing system transferring data in the form of a data stream controlled by said DMA interface controller means, and wherein one respective intermemory link adaptor means of one of said specified central processing systems includes a transmitting buffer established for a specified data stream only and the other respective intermemory link adaptor means of the other specified central processing system includes a receiving buffer established for receiving the said data stream only.

20. In the multiprocessing computer system as recited in claim 19, wherein said DMA interface controller means in each central processing system comprises:

means for generating and responding to a request signal transmitted via said intermemory communication network from one of said central processing systems to another one thereof for establishing a data stream specified by a data transfer request,

interrupt means responsive to said request signal for interrupting the respective central processing system and to generate a stream descriptor defining transfer parameters including free memory space for the storage of data to be transferred by said data stream,

a local control memory associated with said DMA interface controller means for containing a plurality of active stream descriptors, and

interleave means for interleaving transfers of data in accordance with parameters defined by a number of stream descriptors contained in said local control memory.

21. In a multiprocessing computer system as recited in claim 20, wherein said interrupt means responds to the termination of the transfer of the data stream by interrupting the respective central processing system to delete the related stream descriptor contained in said local control memory thereby disengaging the memory space allocated in conjunction with a stream descriptor.

22. In a multiprocessing computer system as recited in claim 19, wherein said DMA interface controller means further comprises speed control means for controlling the rate of transfer of each transferred data stream into said intermemory communication network from respective buffers of respective memory means being specified as a source, thereby ensuring a specified rate of transfer of each of said data streams independently of other data streams into the intermemory communication network and independently of a central processing means.

23. In a multiprocessing computer system as recited in claim 22, wherein said speed control means comprises:

a memory containing an address location defining an entry for each data stream to be transferred, said entries being ordered in groups according to the specified data transfer rates,

scanning means for scanning said entries in one data transfer group at twice the rate of entries in a successive data transfer rate group, and wherein said scanning means performs a fixed number of scans of each entry in the highest data transfer rate group within a specified time period, and

wherein each entry upon being accessed by said scanning means is utilized for initiating a transfer of one data block being part of a data stream and is specified by said DMA interface controller means.

24. A central processing system comprising:

at least one central processing unit having means for processing data in response to instructions and having means for producing address source information, memory means for storing data, bus means interconnecting said memory means and said central process unit, one or more address sourcing devices in addition to said central processing unit including means for controlling transfers of data therebetween on said bus means without intervention by said central processing unit,

at least one group of N+1 peripheral processors, each peripheral processor of said one group arranged to address a respective memory compartment within said memory means, the memory compartments being operatively connected to said bus means,

said central processing system including means for detecting failure of one of said N+1 peripheral processors,

a plurality of N controlled switchover modules, a respective switchover module corresponding to respective peripheral processors except peripheral processor N+1, said switchover modules being responsive to said means for detecting failure,

a plurality of peripheral devices connected respectively via N switchover modules to N peripheral processors when said switchover modules are arranged in a first position, said peripheral processor N+1 not being connected to one of said plurality of peripheral devices when said switchover modules are in said first position, and

said N+1 peripheral processor being connected to the peripheral devices connected to a preselected one of said switchover modules when the preselected switchover module is arranged in a second position.

25. A central processing system as recited in claim 24, wherein each memory compartment in said memory means is connected to the bus means via operatively controlled first bus separators, and

wherein one or more of said memory compartments is further connected to said bus means of another central processing system via operatively controlled second bus separators.

26. An intermemory communication system for providing redundant communication and transfer of data between memories of at least two computer systems, each computer system having at least one central processing unit means for processing data in response to instructions and memory means for storing programs and data, the intermemory communication system comprising:

a plurality of intermemory link means for interconnecting respective memories as part of respective said computer systems, each intermemory link including at least two cables, a plurality of link adaptors for interfacing respective memory means of each of said computer systems, each link adaptor having a pair of tapping means for coupling to one of said intermemory links, one respective tap coupled to one cable of a respective intermemory link, each link adaptor including a receive buffer and a transmit buffer, said transmit buffer including means for indicating a busy status when data are presently stored therein and means for indicating a free status when data have been transferred to an intermemory link, and wherein each link adaptor has arbitrating control means effective to arbitrate the use of an intermemory link common to a plurality of link adaptors, and

DMA interface controller means initiated by a central processing unit in a respective computer system for operatively connecting and transferring a number of data blocks via selected link adaptors and said intermemory link to a preselected computer system defined as a destination computer system without interfering with the central processing units of said respective computer system and said preselected computer system, said DMA interface controller means having means for transferring said number of data blocks to a selected free transmit buffer of a link adaptor operatively connected to the corresponding link adaptor of the destination computer system via a first intermemory link adaptor and being effective to repetitively select another free transmit buffer of a link adaptor being operatively connected to said destination computer system via a different intermemory link until a confirming message has been received from the DMA interface controller means of the destination computer system indicating that the number of data blocks is received valid within a predetermined time period after the transfer of the data blocks to a selected transmit buffer.

27. An intermemory communication system as recited in claim 26, wherein each intermemory link connected to a respective link adaptor including arbitrating control means, respective cables in each said intermemory link defining a transfer path and a respond path, said arbitrating control means comprising:

detector means for producing an idle signal when the transfer path of a respective intermemory link is idle,

delay means enabled when the respective transmit buffer is busy via the busy indicating means, said delay means being responsive to the idle signal to initiate a transfer from said transmit buffer over said transfer path at a pseudorandom period of time after the occurrence of each idle signal,

responding means being effective to direct the data received via the respective transfer path from another link adaptor back to that other link adaptor via the corresponding respond path, and

comparison means for comparing data received via the respond path and data transmitted from the transmit buffer over the corresponding transfer path and being effective to cut off the transfer of data if the compared data are unequal, and to disable said delay means if the compared data are equal.

28. An intermemory communication system as recited in claim 27, wherein said responding means only directs data received via the respective transfer path from another link adaptor path back to that other link adaptor via the corresponding respond path if the receive buffer corresponding to said responding means is ready to receive data.

29. An intermemory communication system as recited in claim 27, wherein said transfer path and said respond path correspond to respective cables for serial bit transmission over said intermemory link.

30. A intermemory communication system as recited in claim 26, wherein each link adaptor electrically senses signals on the intermemory link but is otherwise electrically and mechanically isolated from said intermemory link comprising said intermemory communication network.