Data processor which can repeat the execution of instruction loops with minimal instruction fetches

• US 4,566,063 A
• Filed: 10/17/1983
• Issued: 01/21/1986
• Est. Priority Date: 10/17/1983
• Status: Expired due to Term

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Zolnowsky, John, MacGregor, Douglas B., Eckert, Kim
• Primary Examiner(s): NOT, DEFINED
• Application Number:
  US06/542,800
• Time in Patent Office: 827 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 712/241
• CPC Class Codes: G06F 9/381 Loop buffering
• CPC Class Codes: G06F 9/3861 Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00

Abstract

A pipelined data processor capable of automatically storing in an external memory all essential information relating to the internal state thereof upon the detection of an access fault during instruction execution. Upon correction of the cause of the fault, the data processor automatically retrieves the stored state information and restores the state thereof in accordance with the retrieved state information. The data processor then resumes execution of the instruction. The faulted access may be selectively rerun upon the resumption of instruction execution. In response to detecting a particular sequence of a loopable instruction followed by a conditional branch instruction which selectively branches back to the loopable instruction, the data processor enters a loop mode wherein the loopable instruction and the branch instruction are internally recirculated around the pipeline to save instruction fetch cycles.

Claims

1. A method for selectively repeating the execution of an instruction in a data processor comprising:

an instruction pipeline having at least input and output stages;

bus cycle control means for selectively transferring instructions into the input stage of the pipeline;

pipeline control means for selectively advancing the instructions from the input stage of the pipeline to the output stage thereof; and

instruction execution means for executing the instruction in the output stage of the pipeline;

the method comprising the steps of;

selectively setting a loop control bit;

sequentially enabling the bus cycle control means and the pipeline control means to advance an instruction to the output stage of the pipeline;

enabling the instruction execution means to execute said instruction at the output stage of the pipeline; and

if said loop control bit is set, enabling the pipeline control means to advance the instructions in the pipeline while inserting said instruction into a selected stage of the pipeline.

2. The method of claim 1 including the further step of:

detecting a predetermined instruction at the output stage of said pipeline; and

wherein the step of selectively setting said loop control bit is further defined as selectively setting said loop control bit in response to said predetermined instruction being detected at the output stage of said pipeline.

3. In a data processor comprising:

an instruction pipeline having at least input and output stages;

bus cycle control means for selectively transferring a stream of instructions into the input stage of the pipeline;

pipeline control means for selectively advancing the instructions from the input stage of the pipeline to the output stage thereof; and

instruction execution means for selectively executing each instruction advanced to the output stage of the pipeline, including a conditional branch instruction which specifies a selected branch destination and a selected control condition upon which the branch will be taken;

a method for repeating the execution of a selected loop of the instructions in the stream of instructions with minimal use of the bus cycle control means, comprising the steps of;

(a) detecting the execution by the instruction execution means of one of said conditional branch instructions which specifies a branch destination corresponding to a target instruction preceding the conditional branch instruction in said stream of instructions by no more than the number of stages in the pipeline, the set of instructions between said target instruction and said conditional branch instruction, inclusive, comprising said loop of instructions;

(b) sequentially enabling the bus cycle control means and the pipeline control means to transfer said loop of instructions into the pipeline, and to advance said target instruction to the output stage of the pipeline;

(c) enabling the instruction execution means to execute the instruction at the output stage of the pipeline;

(d) enabling the pipeline control means to advance the instructions in the pipeline while circulating the instruction just executed into a selected stage of the pipeline; and

(e) if the instruction at the output stage of the pipeline is not the conditional branch instruction, returning to step (c);

but

(f) if the instruction at the output stage of the pipeline is the conditional branch instruction and said control condition is not satisfied, enabling the pipeline control means to again advance the instructions in the pipeline while circulating the conditional branch instruction into said selected stage of the pipeline, and then returning to step (c);

whereby the data processor selectively repeats the execution of said loop of instructions by circulating said loop of instructions with said pipeline.

4. In a data processor comprising:

an instruction pipeline having at least input and output stages;

bus cycle control means for selectively transferring instructions into the input stage of the pipeline;

pipeline control means for selectively advancing the instructions from the input stage of the pipeline to the output stage thereof; and

instruction execution means for executing the instruction in the output stage of the pipeline;

the improvement comprising;

means for selectively setting a loop control bit;

means for sequentially enabling the bus cycle control means and the pipeline control means to advance an instruction to the output stage of the pipeline;

means for enabling the instruction execution means to execute said instruction at the output stage of the pipeline; and

means for detecting if said loop control bit is set and, if so, for enabling the pipeline control means to advance the instructions in the pipeline while inserting said instruction into a selected stage of the pipeline.

5. The data processor of claim 4 further including:

means for detecting a predetermined instruction at the output stage of said pipeline; and

wherein the means for selectively setting said loop control bit are further characterized as selectively setting said loop control bit in response to said predetermined instruction being detected at the output stage of said pipeline by said detecting means.