Synchronous clock generator for digital signal multiplex devices
First Claim
1. A synchronous clock generator for digital signal multiplex devices comprising a first counter whose counting period corresponds to a block length of a pulse frame and which can be set into a prescribed counter reading, a block counter controlled by the first counter, and a logic element for generating working clock signals which logic element is connected to the outputs of the counters, characterized in that change-over means are provided for changing the counting period of at least one of the first counter and the block counter to adapt such counting period selectively to a plurality of respective different multiplexers;
- and in that the logic element gates out the working clock signals for such respective different multiplexers according to the condition of said changeover means.
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Accused Products
Abstract
An exemplary embodiment includes a first binary counter whose counting period corresponds to a block length of a pulse frame, a block counter controlled by the first counter, and a logic element for generating working clock signals, wherein the counters are switchable for employment in different multiplex systems and the logic element gates out the working clock signals for different multiplex systems.
24 Citations
9 Claims
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1. A synchronous clock generator for digital signal multiplex devices comprising a first counter whose counting period corresponds to a block length of a pulse frame and which can be set into a prescribed counter reading, a block counter controlled by the first counter, and a logic element for generating working clock signals which logic element is connected to the outputs of the counters, characterized in that change-over means are provided for changing the counting period of at least one of the first counter and the block counter to adapt such counting period selectively to a plurality of respective different multiplexers;
- and in that the logic element gates out the working clock signals for such respective different multiplexers according to the condition of said changeover means.
- View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
Specification