Bit error rate measuring system

• US 4,566,100 A
• Filed: 04/19/1983
• Issued: 01/21/1986
• Est. Priority Date: 04/20/1982
• Status: Expired due to Term

• Current Assignee: Kokusai Denshi Denwa Company Limited (KDDI Corporation)
• Original Assignee: Kokusai Denshi Denwa Company Limited (KDDI Corporation)
• Inventors: Satoh, Gunkichi, Ohkawa, Michihisa, Mizuno, Toshio
• Primary Examiner(s): Fleming, Michael R.
• Application Number:
  US06/486,319
• Time in Patent Office: 1,008 Days
• Field of Search: 371/5, 371/6, 375/86, 375/97, 375/100, 375/52, 375/111, 455/22, 455/316
• US Class Current: 714/704
• CPC Class Codes: H04L 1/206 for modulated signals

Abstract

A bit error rate of M-phase digital phase-modulated waves is measured by the steps comprising multiplying a received wave by M, phase-detecting the M-multiplied signal either directly or after frequency conversion, detecting errors by comparing the output level of the phase detection with a threshold, and counting the number of such errors. By employing above mentioned system, a bit error rate can be measured easily and accurately by a simple circuit structure.

Claims

1. A system for equivalently measuring bit error rate of received M-phase digital phase-modulated waves by steps comprising multiplying a frequency of an M-phase digital phase-modulated wave by M, wherein M is a positive integer, phase-detecting the M-multiplied signal directly or after frequency conversion by using a reference carrier which is orthogonal to a boundary of an error region in a phasor diagram, detecting errors by comparing the phase detection output with a given threshold which is determined so as to correspond to said boundary of the error region, and counting the number of pulses which represent errors.

2. The system for bit error rate measuring as claimed in claim 1, wherein the bit error rate is measured from the number of counted pulses by referring the same to a table of the pulse number vs. bit error rate which has been measured in advance at a receiver side by receiving a data sequence inserted in one of a known pattern, a parity bit and an error correction code at a transmission side.

3. A system for equivalently measuring bit error rate in received M-phase digital phase-modulated waves by steps comprising an M-multiply circuit which multiplies a frequency of an M-phase digital phase-modulated wave by M, wherein M is a positive integer.

a phase detection circuit which phase-detects the output from said M-multiply circuit either directly or after frequency conversion by using a reference carrier which is orthogonal to a boundary of an error region in a phasor diagram,

a discriminating circuit which compares the output level from said phase-detection circuit with a given threshold which is determined so as to correspond to said boundary of the error region and detects errors,

and a counter which counts the output pulses from said discriminating circuit.

4. The system for measuring bit error rate as claimed in claim 3, which further comprises a table of the number of pulses against bit error rate which has been measured in advance at a receiver side by receiving a data sequence inserted in one of a known pattern, a parity bit and an error correction code at a transmission side for comparing the content of the table with the counter output from the counter.

5. The bit error rate measuring system as claimed in claim 3 or 4 which is provided with a band pass filter to pass M-multiplied frequencies at a step prior to the phasedetection circuit.

6. The bit error rate measuring system as claimed in claim 5, which is further provided with a narrow band pass filter to pass M-multiplied frequencies which is coupled to a step subsequent to the M-multiply circuit and a phase shift circuit to correct the phase of the output from said Narrow band pass filter as the means to feed a reference carrier to the phase detection circuit.

7. The bit error rate measuring system as claimed in claim 6 wherein the threshhold of the discriminating circuit is at 0 level.

8. The bit error rate measuring system as claimed in claim 5 wherein the threshhold of the discriminating circuit is at 0 level.

9. The bit error rate measuring system as claimed in claim 3, or 4 which is further provided with a narrow band pass filter to pass M-multiplied frequencies which is coupled to a step subsequent to the M-multiply circuit and a phase shift circuit to correct the phase of the output from said filter as the means to feed a reference carrier to the phase detection circuit.

10. The bit error rate measuring system as claimed in claim 9 wherein the threshhold of the discriminating circuit is at 0 level.

11. The bit error rate measuring system as claimed in claim 3 or 4 which is provided with a frequency down converter at a step subsequent to the M-multiply circuit, another phase detection circuit which detects the phase difference between the signals input to the phase detection circuit and the reference carrier, and a voltage control oscillator of which oscillation frequency is controlled by the output from said detection circuit.

12. The bit error rate measuring system as claimed in claim 11 which is further provided as a means to generate a reference carrier with a narrow band pass filter coupled to a step subsequent to the down converter and a phase shift circuit to correct the phase of the output from said filter.

13. The bit error rate measuring system as claimed in claim 12 wherein the threshhold of the discriminating circuit is at 0 level.

14. The bit error rate measuring system as claimed in claim 11 wherein the threshhold of the discriminating circuit is at 0 level.

15. The bit error rate measuring system as claimed in claim 3 or 4, wherein the threshhold of the discriminating circuit is at 0 level.