Automatic character recognition system

• US 4,567,609 A
• Filed: 03/28/1983
• Issued: 01/28/1986
• Est. Priority Date: 03/28/1983
• Status: Expired due to Fees

• Current Assignee: the united states of america as represented by the secretary of the navy
• Original Assignee: the united states of america as represented by the secretary of the navy
• Inventors: Metcalf, Travis W.
• Primary Examiner(s): Boudreau, Leo H.
• Application Number:
  US06/479,372
• Time in Patent Office: 1,037 Days
• Field of Search: 382/9, 382/32, 382/48, 382/52, 382/34
• US Class Current: 382/105
• CPC Class Codes: G06V 10/88 Image or video recognition using optical means, e.g. reference filters, holographic masks, frequency domain filters or spatial domain filters
• CPC Class Codes: G06V 30/10 Character recognition
• CPC Class Codes: G06V 30/146 Aligning or centring of the image pick-up or image-field
• CPC Class Codes: G06V 30/162 Quantising the image signal

Abstract

An apparatus and method for automatic character recognition is presented ch automatically locates and recognizes alphanumeric characters in a scene viewed by a raster-scan type of sensor. By this method the apparatus can search the entire scene and recognize up to seven alphanumeric characters in a bounded area of known size by the correlation technique in less than 1.5 seconds. The technique used first locates the bounded area and alphanumeric characters and then performs the recognition. Two different feature extraction methods are used to locate the characters in the scene. The recognition function is performed by correlation using an incoherent electrooptical processor.

Claims

1. An apparatus for automatic location and recognition of alphanumeric characters in a bounded area of known size within a scene viewed by a raster-scan type video sensor which comprises:

means, connected to receive a video signal from the raster-scanned type sensor, for converting said video signal into a digital binary signal whereby the alphanumeric characters are represented by one of the binary signals and the background data is represented by the other binary signal;

means, disposed to receive the output of the converting means, for locating a known bounded area containing alphanumeric characters in the scene viewed;

means, connected to the locating means, for recognizing the alphanumeric characters contained in the known bounded area; and

means, disposed to receive the output of the recognizing means, for further processing and displaying of the recognized alphanumeric characters;

wherein the converting means comprises;

means, disposed to receive the analog video signal from the video sensor, for presearching the scene viewed to locate probable bounded areas containing alphanumeric characters, wherein said means for presearching identifies horizontal and vertical coordinates representing the location of each probable bounded area containing alphanumeric characters;

means, connected to receive a signal from the output of the presearching means, for setting a threshold to represent the background signal level;

means, connected to the presearching means, for storing the horizontal and vertical coordinates representing the location of each probable bounded area containing alphanumeric characters; and

means, connected to receive the analog video signal from the video sensor and also connected to receive the output analog signal from the threshold setting means, for digitizing those signals pertaining to probable bounded areas containing alphanumeric characters in a manner that signals pertaining to alphanumeric characters are set as a first binary coded signal level and the background signals are set at the second binary coded signal level;

the apparatus further comprising;

a threshold setting means which adjusts the threshold reference signal to relate in an absolute manner to analog signals pertaining to probable alphanumeric characters in a manner that possible alphanumeric characters are always treated similarly in relation to the background level whether the alphanumeric characters are light colored on a dark background or dark colored on a light background; and

an analog comparator as the digitizing means, said analog comparator outputting a digital logic binary signal of "1" for data pertaining to alphanumeric characters and a digital logic signal of "0" for data caused by background signals;

wherein the presearching means comprises;

an input for receiving the video signals from the video sensor;

a bit clock generator;

a first analog delay circuit connected to receive the video sensor input, said delay circuit causing a delay of time length equal to one horizontal video line scan;

a first analog differential comparator which receives input signals from the first analog delay circuit and from the video sensor input, said comparator outputting a signal when the input signals differ;

a first AND gate which receives one input from the bit clock generator and a second input from the output of the first analog differential comparator, said AND gate emitting an output signal when signals occur simultaneously at both inputs;

a first counter connected to receive the output of the first AND gate, said counter accumulating a total count representing the period during which the first AND gate is outputting a pulse signal;

a first digital comparator connected to receive the count output (A) from the first counter and to compare this accumulating count against a preset test count (B) which represents the expected horizontal width of a single alphanumeric character, said comparator outputting a signal when A is less than or equal to B;

a first D-flip flop unit connected to receive the output signal from the first digital comparator, said flip flop unit outputs a signal after it has been triggered by a first output signal from the first digital converter;

a second D-flip flop unit connected to receive the output of the first D-flip flop unit and to receive the output signals from the first digital comparator, said second D-flip flop unit being activated by the output signal from the first D-flip flop unit which occurs when the first flip flop unit is activated by the first output signal emitted from the first comparator, and then is caused to emit a signal at its output when a second consecutive signal is emitted from the first comparator;

a second counter connected to receive inputs from the bit clock generator which causes the counter to accumulate counts;

a second digital comparator connected to receive the count output (C) from the second counter, and to compare this accumulating count against a preset test count (D) which represents the expected horizontal width of the area containing all alphanumeric characters of interest, said comparator outputting a signal when C is greater than or equal to D;

a second AND gate which receives inputs from the second digital comparator and the second D-flip flop unit, said AND gate emitting an output signal when its input'"'"'s both simultaneously hold an input signal, whereby the tentative detection of a field of alphanumeric characters of interest against a clear background has been accomplished;

a second analog delay circuit connected to receive the output of the first analog delay circuit, said second circuit causing a delay of time length equal to 10 bits along a horizontal video line scan;

a second analog differential comparator connected to receive the output of the second analog delay circuit and the output of the first analog delay circuit, said second analog differential comparator outputting a signal when its input signals differ, said second differential comparator being connected to feed this output signal to the second counter and the first and second D-flip flop units whereby these respective devices are reset to restart their active functions over;

a first OR gate connected to receive the output signals from the first and second analog differential comparators, said OR gate emitting a signal when either of the signals input from said first and second comparators exist, and said output of the OR gate connected to the first counter whereby this counter is reset to the start position when a signal from the OR gate output occurs; and

a third analog delay circuit connected to receive the output video signal from said first analog delay circuit, said third delay circuit causing a delay of time length equal to one horizontal video line scan.

2. An apparatus according to claim 1 wherein the means for setting a threshold comprises:

a third counter connected to receive the output of the converting means, said counter being activated to reset its count level upon the reception of an output signal from the converting means, and said counter also disposed to receive a horizontal line scan synchronizing signal from the video sensor for reseting said counter at the beginning of each TV line scan;

a decoder connected to receive the output of the converting means and the output of the third counter, said decoder serving to pass the signal from the converting means to one of a plurality of its outputs as selected by the count setting on the counter;

a plurality of sample and hold circuits, each said circuit separately connected to receive output signals from said decoder in a manner as prescribed by the count on said third counter whereby said received signals from the decoder controls activation of the sample and hold circuits, and each said sample and hold circuit being separately connected to receive the video signal from the output of the third analog delay circuit in the converting means, whereby the analog voltage level of the video signal is stored in the preselected activated sample and hold circuit; and

an analog multiplexer connected to receive the outputs of each said sample and hold circuits, and connected to receive control signals from the means for storing the horizontal and vertical coordinates, said multiplexer outputting the video voltage level signal from the proper sample and hold circuit when directed by the received control signal from the storing means.

3. An apparatus according to claim 2 wherein the means for storing the horizontal and vertical coordinates representing the location of each possible bounded area containing alphanumeric characters comprises:

a fourth counter connected to receive the horizontal line scan synchronizing signal from the video sensor for incrementing said counter one count at the beginning of each TV line scan;

a first RAM connected to receive and store the output count of the fourth counter, and connected to receive the output signal from the second AND gate within the presearching means which, when received, causes the last stored count in said counter to be outputted to the means for locating the bounded area containing alphanumeric characters;

a fifth counter connected to receive the output of the bit clock generator for causing said counter to index counts related to the linear position on a horizontal TV scan line, and connected to receive the horizontal line scan synchronizing signal from the video sensor for reseting said counter to restart at the beginning of each horizontal TV scan line;

a subtractor connected to receive the count from said fifth counter and also connected to receive the output signal from the second AND gate within the presearching means, said subtractor causing the preset test count D to be subtracted from the count in said fifth counter upon the receipt of the output signal from the second AND gate;

a second RAM connected to receive the output count from the subtractor, said RAM storing the count which represents the horizontal position of the left edge of the bounded area containing alphanumeric characters;

a third digital comparator connected to receive the output of the second RAM, this output being the last count (F) stored in the second RAM, and connected to receive the accumulated count of the fifth counter (E), said third comparator outputting a signal when E=F with one connection of this output back to the second RAM whereby said RAM is address incremented upon the occurrence of the output signal; and

a sixth counter connected to the output of the third digital comparator whereby said counter is indexed one count for each signal emitted by the third digital comparator, said counter also connected to receive the horizontal line scan synchronizing signal from the video sensor for reseting said counter upon receipt of this signal at the beginning of each TV line scan, and the output of said sixth counter connected to the analog multiplexer within the threshold setting means for causing the proper sample and hold circuit to be outputted through the multiplexer.

4. An apparatus according to claim 3 wherein the digitizing means comprises:

a third analog delay circuit, connected to receive the output video signal of the first analog delay circuit within the presearching means, for further delaying the input video signal for a time period equal to one horizontal video line scans; and

a third analog differential comparator with one input connected to the output of the third analog delay circuit and a second input connected to the output of the means for setting a threshold, said comparator emitting a quantized digital binary signal with a logic signal of "1" for data pertaining to possible alphanumeric characters and the logic signal "0" for data caused by the background.

5. An apparatus according to claim 4 wherein the locating means comprises:

means, connected to receive quantized binary data signals from the converting means, for holding said quantized data for each bounded area scene pertaining to a possible alphanumeric character field;

means, connected to receive the output of the holding means, for multiplexing in an ordered way the signal output from said holding means; and

means, connected to the multiplexing means, for controlling the multiplexing means operation, said controlling means also connected to receive data from the holding means and the converting means, to process this data and to emit control signals to the holding means.

6. An apparatus according to claim 5 wherein the locating means further comprises:

a plurality of OR gates connected between the holding means and the controlling means, said OR gates established to receive preselected groups of data output from the holding means, and to emit a resultant signal to the controlling means.

7. An apparatus according to claim 6 wherein the holding means comprises:

a third RAM connected to the output of the converting means to receive and store each bounded scene of quantized video data, said RAM also connected to the controlling means for receiving command signals;

an address encoder connected to receive counts from the bit clock generator; and

an address selector connected to receive data and command signals from the controlling means, said address selector connected to output address data to the third RAM when commanded by the controlling means.

8. An apparatus according to claim 7 wherein the controlling means comprises:

a microcomputer.

9. An apparatus according to claim 8 wherein the recognizing means comprises:

an electrooptical processor (EOP) connected to receive from the multiplexing means prearranged streams of the quantized data; and

a correlation peak detector connected to the output of the electro-optical processor.

10. An apparatus according to claim 9 wherein the EOP comprises:

a first summing circuit which is connected to the output for multiplexing means, said summing circuit sums the quantized data elements;

an averaging circuit to divide the first summing circuits output by a preset number representing the total elements of data in the scene area containing an alphanumeric character;

a digital delay circuit connected to the output of the multiplexing means, said delay circuit causing a delay to the data stream equal to the present number which is the divisor for the averaging circuit;

a second summing circuit connected to the outputs of the averaging circuit and the digital delay circuit, and also connected to receive a preset bias signal, said second summing circuit preset to combine these signals in a preselected manner;

a light emitting diode (LED) connected to the output of the second summing circuit, said LED converting the electrical signal into a scanning light signal;

a mask fixed to intercept the scanning light signal emitted by the LED, said mask constructed with a preselected arrangement of transparent openings to allow the passage of the scanning light signal in a manner that maximum intensity occurs when the opening arrangements correspond with peaks in the scanning light signal;

a charged coupled device (CCD) positioned behind the work mask opposite the LED, said CCD disposed to receive the transmitted light signals whereby the transmitted light intensity is measured and electrically stored; and

a shift register connected to the CCD to collect accumulated electrical signals of preselected groups of openings in the preselected arrangement of transparent openings which represent the light intensity of these groups in the CCD.

11. An apparatus according to claim 10 wherein the correlation peak detector comprises:

an analog to digital (A/D) converter connected to receive and convert the analog signal output from the shift register;

means, connected to receive the digitized signal from the A/D converter, for determining the preselected group of openings whose accumulated signal has the highest correlation level; and

means, connected to the determining means and the EOP for identifying which alphanumeric character is associated with the preselected group of openings showing the highest correlated signal level.

12. An apparatus according to claim 11 wherein the determining means comprises:

a sixth counter connected to receive a horizontal clock pulse signal from the EOP;

a fourth digital comparator connected to receive the output count (G) from the sixth counter and a preset count level (H), said comparator emitting at its output a command signal when G=H;

a first latch connected to the output of the A/D converter and to the output of the fourth digital comparator, said latch commanded to the hold output signal of the A/D converter by the output command signal from said fourth digital comparator;

a digital subtractor with inputs connected to the outputs of the first latch and the A/D converter, said digital subtractor removing from the digitized signal emitted at the output of the A/D converter a preset amount of signal;

a second latch connected to the output of the digital subtractor, said second latch storing the output of the digital subtractor until commanded to restore a newer output value from the digital subtractor;

a fifth digital comparator connected to receive the real time output count value (J) from the digital subtractor and to receive the output count value (K) stored in the second latch, said comparator emitting a control signal at its output when J is greater than K, said control signal output connected to the second latch for providing the command for storing the newer output value (J) from the digital subtractor;

a sixth digital comparator connected at its inputs to receive the output count value (K) of the second latch and a preset minimum limit level value (L), said comparator emitting at its output a control signal; and

a third latch connected to receive the count (G) from the sixth counter, and connected to receive control signals from the outputs of the fifth and sixth comparators, said control signal from the sixth comparator causing said latch to be unable to emit through its output any data signal when K is less than L, and said control signal from the fifth comparator commanding said latch to output the data count if not inhibited by the sixth comparator control.

13. An apparatus according to claim 1 wherein the locating means comprises:

means, connected to receive quantized binary data signals from the converting means, for holding said quantized data for each bounded area scene pertaining to a possible alphanumeric character field;

means, connected to receive the output of the holding means, for multiplexing in an ordered way the signal output from said holding means; and

means, connected to the multiplexing means, for controlling the multiplexing means operation, said controlling means also connected to receive data from the holding means and the converting means, to process this data and to emit control signals to the holding means.

14. An apparatus according to claim 13 wherein the recognizing means comprises:

an electrooptical processor (EOP) connected to receive from the multiplexing means prearranged streams of the quantized data; and

a correlation peak detector connected to the output of the electro-optical processor.

15. An apparatus according to claim 14 wherein the EOP comprises:

a first summing circuit which is connected to the output of the multiplexing means, said summing circuit sums the quantized data elements;

an averaging circuit to divide the first summing circuits output by a preset number representing the total elements of data in the scene area containing an alphanumeric character;

a digital delay circuit connected to the output of the multiplexing means, said delay circuit causing a delay to the data stream equal to the preset number which is the divisor for the averaging circuit;

a second summing circuit connected to the outputs of the averaging circuit and the digital delay circuit, and also connected to receive a preset bias signal, said second summing circuit preset to combine these signals in a preselected manner;

a light emitting diode (LED) connected to the output of the second summing circuit, said LED converting the electrical signal into a scanning light signal;

a mask fixed to intercept the scanning light signal emitted by the LED, said mask constructed with a preselected arrangement of transparent openings to allow the passage of the scanning light signal in a manner that maximum intensity occurs when the opening arrangements correspond with peaks in the scanning light signal;

a charged coupled device (CCD) positioned behind the work mask opposite the LED, said CCD disposed to receive the transmitted light signals whereby the transmitted light intensity is measured and electrically stored; and

a shift register connected to the CCD to collect accumulated electrical signals of preselected groups of openings in the preselected arrangement of transparent openings which represent the light intensity of these groups in the CCD.

16. An apparatus according to claim 15 wherein the correlation peak detector comprises:

an analog to digital (A/D) converter connected to receive and convert the analog signal output from the shift register;

means, connected to receive the digitized signal from the A/D converter, for determining the preselected group of openings whose accumulated signal has the highest correlation level; and

means, connected to the determining means and the EOP for identifying which alphanumeric character is associated with the preselected group of openings showing the highest correlated signal level.

17. An apparatus according to claim 16 wherein the determining means comprises:

a sixth counter connected to receive a horizontal clock pulse signal from the EOP;

a fourth digital comparator connected to receive the output count (G) from the sixth counter and a preset count level (H), said comparator emitting at its output a command signal when G=H;

a first latch connected to the output of the A/D converter and to the output of the fourth digital comparator, said latch commanded to hold the output signal of the A/D converter by the output command signal from said fourth digital comparator;

a digital subtractor with inputs connected to the outputs of the first latch and the A/D converter, said digital subtractor removing from the digitized signal emitted at the output of the A/D converter a preset amount of signal;

a second latch connected to the output of the digital subtractor, said second latch storing the output of the digital subtractor until commanded to restore a newer output value from the digital subtractor;

a fifth digital comparator connected to receive the real time output count value (J) from the digital subtractor and to receive the output count value (K) stored in the second latch, said comparator emitting a control signal at its output when J is greater than K, said control signal output connected to the second latch for providing the command for storing the newer output value (J) from the digital subtractor;

a sixth digital comparator connected at its inputs to receive the output count value (K) of the second latch and a preset minimum limit level value (L), said comparator emitting at its output a control signal; and

a third latch connected to receive the count (G) from the sixth counter, and connected to receive control signals from the outputs of the fifth and sixth comparators, said control signal from the sixth comparator causing said latch to be unable to emit through its output any data signal when K is less than L, and said control signal from the fifth comparator commanding said latch to output the data count if not inhibited by the sixth comparator control.

18. An apparatus according to claim 1 wherein the recognizing means comprises:

an electrooptical processor (EOP) connected to receive from the multiplexing means prearranged streams of the quantized data; and

a correlation peak detector connected to the output of the electro-optical processor.

19. An apparatus according to claim 18 further including:

said threshold setting means which adjusts a threshold reference signal to relate in an absolute manner to analog signals pertaining to probable alphanumeric characters in a manner that possible alphanumeric characters are always treated similarly in relation to the background level whether the alphanumeric characters are light colored on a dark background or dark colored on a light background; and

an analog comparator as the digitizing means, said analog comparator outputing a digital logic binary signal of "1" for data pertaining to alphanumeric characters and a digital logic signal of "0" for data caused by background signals.

20. An apparatus according to claim 19 wherein the presearching means comprises:

an input for receiving video signals from the video sensor;

a bit clock generator;

a first analog delay circuit connected to receive the video sensor input, said delay circuit causing a delay of time length equal to one horizontal video line scan;

a first analog differential comparator which receives input signals from the first analog delay circuit and from the video sensor input, said comparator outputting a signal when the input signals differ;

a first AND gate which receives one input from the bit clock generator and a second input from the output of the first analog differential comparator, said AND gate emitting an output signal when signals occur simultaneously at both inputs;

a first counter connected to receive the output of the first AND gate, said counter accumulating a total count representing the period during which the first AND gate is outputing a pulsed signal;

a first digital comparator connected to receive the count output (A) from the first counter and to compare this accumulating count against a preset test count (B) which represents the expected horizontal width of a single alphanumeric character, said comparator outputing a signal when A is less than or equal to B;

a first D-flip flop unit connected to receive the output signal from the first digital comparator, said flip flop unit outputs a signal after it has been triggered by a first output signal from the first digital converter;

a second D-flip flop unit connected to receive the output of the first D-flip flop unit and to receive the output signals from the first digital comparator, said second D-flip flop unit being activated by the output signal from the first D-flip flop unit which occurs when the first flip flop unit is activated by the first output signal emitted from the first comparator, and then is caused to emit a signal at its output when a second consecutive signal is emitted from the first comparator;

a second counter connected to receive inputs from the bit clock generator which causes the counter to accumulate counts;

a second digital comparator connected to receive the count output (C) from the second counter, and to compare this accumulating count against a preset test count (D) which represents the expected horizontal width of the area containing all alphanumeric characters of interest, said comparator outputting a signal when C is greater than or equal to D;

a second AND gate which receives inputs from the second digital comparator and the D-flip flop unit, said AND gate emitting an output signal when its input'"'"'s both simultaneously hold an input signal, whereby the tentative detection of a field of alphanumeric characters of interest against a clear background has been accomplished;

a second analog delay circuit connected to receive the output of the first analog delay circuit, said second circuit causing a delay of time length equal to 10 bits along a horizontal video line scan;

a second analog differential comparator connected to receive the output of the second analog delay circuit and the output of the first analog delay circuit, said second analog differential comparator outputting a signal when its input signals differ, said second differential comparator being connected to feed this output signal to the second counter and the first and second D-flip flop units whereby these respective devices are reset to restart their active functions over;

a first OR gate connected to receive the output signals from the first and second analog differential comparators, said OR gate emitting a gate signal when either of the signals input from said first and second comparators exist, and said output of the OR gate connected to the first counter whereby this counter is reset to the start position when a signal from the OR gate output occurs; and

a third analog delay circuit connected to receive the output video signal from said first analog delay circuit, said third delay circuit causing a delay of time length equal to one horizontal video line scan.

21. An apparatus according to claim 20 wherein the means for setting a threshold comprises:

a third counter connected to receive the output of the converting means, said counter being activated to reset its count level upon the reception of an output signal from the converting means, and said counter also disposed to receive a horizontal line scan synchronizing signal from the video sensor for reseting said counter at the beginning of each TV line scan;

a decoder connected to receive the output of the converting means and the output of the third counter, said decoder serving to pass the signal from the converting means to one of a plurality of its outputs as selected by the count setting on the counter;

a plurality of sample and hold circuits, each said circuit separately connected to receive output signals from said decoder in a manner as prescribed by the count on said third counter whereby said received signals from the decoder controls activation of the sample and hold circuits, and each said sample and hold circuit being separately connected to receive the video signal from the output of the third analog delay circuit in the converting means, whereby the analog voltage level of the video signal is stored in the preselected activated sample and hold circuit; and

an analog multiplexer connected to receive the outputs of each said sample and hold circuits, and connected to receive control signals from the means for storing the horizontal and vertical coordinates, said multiplexer outputting the video voltage level signal from the proper sample and hold circuit when directed by the received control signal from the storing means.

22. An apparatus according to claim 21 wherein the means for storing the horizontal and vertical coordinates representing the location of each possible bounded area containing alphanumeric characters comprises:

a fourth counter connected to receive the horizontal line scan synchronizing signal from the video sensor for incrementing said counter one count at the beginning of each TV line scan;

a first RAM connected to receive and store the output count of the fourth counter, and connected to receive the output signal from the second AND gate within the presearching means which, when received, causes the last stored count in said counter to be outputted to the means for locating the bounded area containing alphanumeric characters;

a fifth counter connected to receive the output of the bit clock generator for causing said counter to index counts related to the linear position on a horizontal TV scan line, and connected to receive the horizontal line scan synchronizing signal from the video sensor for reseting said counter to restart at the beginning of each horizontal TV scan line;

a subtractor connected to receive the count from said fifth counter and also connected to receive the output signal from the second AND gate within the presearching means, said subtractor causing the preset test count D to be subtracted from the count in said fifth counter upon the receipt of the output signal from the second AND gate;

a second RAM connected to receive the output count from the subtractor, said RAM storing the count which represents the horizontal position of the left edge of the bounded area countaing alphanumeric characters;

a third digital comparator connected to receive the output of the second RAM, this output being the last count (F) stored in the second RAM, and connected to receive the accumulated count of the fifth counter (E), said third comparator outputting a signal when E=F with one connection of this output back to the second RAM whereby said RAM is address incremented upon the occurrence of the output signal; and

a sixth counter connected to the output of the third digital comparator whereby said counter is indexed one count for each signal emitted by the third digital comparator, said counter also connected to receive the horizontal line scan synchronizing signal from the video sensor for reseting said counter upon receipt of this signal at the begining of each TV line scan, and the output of said sixth counter connected to the analog multiplexer within the threshold setting means for causing the proper sample and hold circuit to be outputted through the multiplexer.

23. An apparatus according to claim 22 wherein the digitizing means comprises:

a third analog delay circuit, connected to receive the output video signal of the first analog delay circuit within the presearching means, for further delaying the input video signal for a time period equal to one horizontal video line scans; and

a third analog differential comparator with one input connected to the output of the third analog delay circuit and a second input connected to the output of the means for setting a threshold, said comparator emitting a quantized digital binary signal with a logic signal of "1" for data pertaining to possible alphanumeric characters and the logic signal of "0" for data caused by the background;

output of the fourth digital comparator, said latch commanded to hold the output signal of the A/D converter by the output command signal from said fourth digital comparator;

a digital subtractor with inputs connected to the outputs of the first latch and the A/D converter, said digital subtractor removing from the digitized signal emitted at the output of the A/D converter a preset amount of signal;

a second latch connected to the output of the digital subtractor, said second latch storing the output of the digital subtractor until commanded to restore a newer output value from the digital subtractor;

a fifth digital comparator connected to receive the real time output count value (J) from the digital subtractor and to receive the output count value (K) stored in the second latch, said comparator emitting a control signal at its output when J is greater than K, said control signal output connected to the second latch for providing the command for storing the newer output value (J) from the digital subtractor;

a sixth digital comparator connected at its inputs to receive the output count value (K) of the second latch and a preset minimum limit level value (L), said comparator emitting as its output a control signal; and

a third latch connected to receive the count (G) from the sixth counter, and connected to receive control signals from the outputs of the fifth and sixth comparators, said control signal from the sixth comparator causing said latch to be unable to emit through its output any data signal when K is less than L, and said control signal from the fifth comparator commanding said latch to output the data count if not inhibited by the sixth comparator control.

24. An apparatus according to claim 23 wherein the EOP comprises:

a first summing circuit which is connected to the output of the multiplexing means, said summing circuit sums the quantized data elements;

an averaging circuit to divide the first summing circuits output by a preset number representing the total elements of data in the scene area containing an alphanumeric character;

a digital delay circuit connected to the output of the multiplexing means, said delay circuit causing a delay to the data stream equal to the present number which is the divisor for the averaging circuit;

a second summing circuit connected to the outputs of the averaging circuit and the digital delay circuit, and also connected to receive a preset bias signal, said second summing circuit preset to combine these signals in a preselected manner;

a light emitting diode (LED) connected to the output of the second summing circuit, said LED converting the electrical signal into a scanning light signal;

a mask fixed to intercept the scanning light signal emitted by the LED, said mask constructed with a preselected arrangement of transparent openings to allow the passage of the scanning light signal in a manner that maximum intensity occurs when the opening arrangements correspond with peaks in the scanning light signal;

a charged coupled device (CCD) positioned behind the work mask opposite the LED, said CCD disposed to receive the transmitted light signals whereby the transmitted light intensity is measured and electrically stored; and

a shift register connected to the CCD to collect accumulated electrical signals of preselected groups of openings in the preselected arrangement of transparent openings which represent the light intensity of these groups in the CCD.

25. An apparatus according to claim 24 wherein the correlation peak detector comprises:

an analog to digital (A/D) converter connected to receive and convert the analog signal output from the shift register;

means, connected to receive the digitized signal from the A/D converter, for determining the preselected group of openings whose accumulated signal has the highest correlation level; and

means, connected to the determining means and the EOP for identifying which alphanumeric character is associated with the preselected group of openings showing the highest correlated signal level.

26. An apparatus according to claim 25 wherein the determining means comprises:

a sixth counter connected to receive a horizontal clock pulse signal from the EOP;

a fourth digital comparator connected to receive the output count (G) from the sixth counter and a preset count level (H), said comparator emitting at its output a command signal when G=H;

a first latch connected to the output of the A/D converter and to the output of the fourth digital comparator, said latch commanded to hold the output signal of the A/D converter by the output command signal from said fourth digital comparator;

a digital subtractor with inputs connected to the outputs of the first latch and the A/D converter, said digital subtractor removing from the digitized signal emitted at the output of the A/D converter a preset amount of signal;

a second latch connected to the output of the digital subtractor, said second latch storing the output of the digital subtractor until commanded to restore a newer output value from the digital subtractor;

a fifth digital comparator connected to receive the real time output count value (J) from the digital subtractor and to receive the output count value (K) stored in the second latch, said comparator emitting a control signal at its output when J is greater than K, said control signal output connected to the second latch for providing the command for storing the newer output value (J) from the digital subtractor;

a sixth digital comparator connected at its inputs to receive the output count value (K) of the second latch and a preset minimum limit level value (L), said comparator emitting at its output a control signal; and

a third latch connected to receive the count (G) from the sixth counter, and connected to receive control signals from the outputs of the fifth and sixth comparators, said control signal from the sixth comparator causing said latch to be unable to emit through its output any data signal when K is less than L, and said control signal from the fifth comparator commanding said latch to output the data count if not inhibited by the sixth comparator control.

27. An apparatus according to claim 1 wherein the locating means comprises:

means, connected to receive quantized binary data signals from the converting means, for holding said quantized data for each bounded area scene pertaining to a possible alphanumeric character field;

means, connected to receive the output of the holding means, for multiplexing in an ordered way the signal output from said holding means; and

means, connected to the multiplexing means, for controlling the multiplexing means operation, said controlling means also connected to receive data from the holding means and the converting means, to process this data and to emit control signals to the holding means.

28. An apparatus according to claim 27 wherein the recognizing means comprises:

an electrooptical processor (EOP) connected to receive from the multiplexing means prearranged streams of the quantized data; and

a correlation peak detector connected to the output of the electro-optical processor.

29. An apparatus according to claim 28 wherein the locating means further comprises:

a plurality of OR gates connected between the holding means and the controlling means, said OR gates established to receive preselected groups of data output from the holding means, and to emit a resultant signal to the controlling means.

30. An apparatus according to claim 29 wherein the holding means comprises:

a third RAM connected to the output of the converting means to receive and store each bounded scene of quantized video data, said RAM also connected to the controlling means for receiving command signals;

an address encoder connected to receive counts from the bit clock generator; and

an address selector connected to receive data and command signals from the controlling means, said address selector connected to output address data to the third RAM when commanded by the controlling means.

31. An apparatus according to claim 30 wherein the controlling means comprises:

a microcomputer.

32. An apparatus according to claim 31 wherein the EOP comprises:

a first summing circuit which is connected to the output of the multiplexing means, said summing circuit sums the quantized data elements;

an averaging circuit to divide the first summing circuits output by a preset number representing the total elements of data in the scene area containing an alphanumeric character;

a digital delay circuit connected to the output of the multiplexing means, said delay circuit causing a delay to the data stream equal to the preset number which is the divisor for the averaging circuit;

a second summing circuit connected to the outputs of the averaging circuit and the digital delay circuit, and also connected to receive a preset bias signal, said second summing circuit preset to combine these signals in a preselected manner;

a light emitting diode (LED) connected to the output of the second summing circuit, said LED converting the electrical signal into a scanning light signal;

a mask fixed to intercept the scanning light signal emitted by the LED, said mask constructed with a preselected arrangement of transparent openings to allow the passage of the scanning light signal in a manner that maximum intensity occurs when the opening arrangements correspond with peaks in the scanning light signal;

a charged coupled device (CCD) positioned behind the work mask opposite the LED, said CCD disposed to receive the transmitted light signals whereby the transmitted light intensity is measured and electrically stored; and

a shift register connected to the CCD to collect accumulated electrical signals of preselected groups of openings in the preselected arrangement of transparent openings which represent the light intensity of these groups in the CCD.

33. An apparatus according to claim 32 wherein the correlation peak detector comprises:

an analog to digital (A/D) converter connected to receive and convert the analog signal output from the shift register;

means, connected to receive the digitized signal from the A/D converter, for determining the preselected group of openings whose accumulated signal has the highest correlation level; and

means, connected to the determining means and the EOP for identifying which alphanumeric character is associated with the preselected group of openings showing the highest correlated signal level.

34. An apparatus according to claim 33 wherein the determining means comprises:

a sixth counter connected to receive a horizontal clock pulse signal from the EOP;

a fourth digital comparator connected to receive the output count (G) from the sixth counter and a preset count level (H), said comparator emitting at its output a command signal when G=H;

a first latch connected to the output of the A/D converter and to the output of the fourth digital comparator, said latch commanded to hold the output signal of the A/D converter by the output command signal from said fourth digital comparator;

a digital subtractor with inputs connected to the outputs of the first latch and the A/D converter, said digital subtractor removing from the digitized signal emitted at the output of the A/D converter a preset amount of signal;

a second latch connected to the output of the digital subtractor, said second latch storing the output of the digital subtractor until commanded to restore a newer output value from the digital subtractor;

a fifth digital comparator connected to receive the real time output count value (J) from the digital subtractor and to receive the output count value (K) stored in the second latch, said comparator emitting a control signal at its output when J is greater than K, said control signal output connected to the second latch for providing the command for storing the newer output value (J) from the digital subtractor;

a sixth digital comparator connected at its inputs to receive the output count value (K) of the second latch and a preset minimum limit level value (L), said comparator emitting at its output a control signal; and

a third latch connected to receive the count (G) from the sixth counter, and connected to receive control signals from the outputs of the fifth and sixth comparators, said control signal from the sixth comparator causing said latch to be unable to emit through its output any data signal when K is less than L, and said control signal from the fifth comparator commanding said latch to output the data count if not inhibited by the sixth comparator control.

35. An apparatus according to claim 1 wherein the recognizing means comprises:

an electrooptical processor (EOP) connected to receive from the multiplexing means prearranged streams of the quantized data; and

a correlation peak detector connected to the output of the electro-optical processor.

36. An apparatus according to claim 35 wherein the converting means comprises:

means, disposed to receive the analog video signal from the video sensor, for presearching the scene viewed to locate probable bounded areas containing alphanumeric characters, wherein said means for presearching identifies horizontal and vertical coordinates representing the location of each probable bounded area containing alphanumeric characters;

means, connected to receive a signal from the output of the presearching means, for setting a threshold to represent the background signal level;

means, connected to the presearching means, for storing the horizontal and vertical coordinates representing the location of each probable bounded area containing alphanumeric characters; and

means, connected to receive the analog video signal from the video sensor and also connected to receive the output analog signal from the threshold setting means, for digitizing those signals pertaining to probable bounded areas containing alphanumeric characters in a manner that signals pertaining to alphanumeric characters are set at a first binary coded signal level and the background signals are set at the second binary coded signal level.

37. An apparatus according to claim 36 wherein the locating means comprises:

means, connected to receive quantized binary data signals from the converting means, for holding said quantized data for each bounded area scene pertaining to a possible alphanumeric character field;

means, connected to receive the output of the holding means, for multiplexing in an ordered way the signal output from said holding means; and

means, connected to the multiplexing means, for controlling the multiplexing means operation, said controlling means also connected to receive data from the holding means and the converting means, to process this data and to emit control signals to the holding means.

38. An apparatus according to claim 37 further including:

said threshold setting means which adjusts a threshold reference signal to relate in an absolute manner to analog signals pertaining to probable alphanumeric characters in a manner that possible alphanumeric characters are always treated similarly in relation to the background level whether the alphanumeric characters are light colored on a dark background or dark colored on a light background; and

an analog comparator as the digitizing means, said analog comparator outputing a digital logic binary signal of "1" for data pertaining to alphanumeric characters and a digital logic signal of "0" for data caused by background signals.

39. An apparatus according to claim 38 wherein the locating means further comprises:

a plurality of OR gates connected between the holding means and the controlling means, said OR gates established to receive preselected groups of data output from the holding means, and to emit a resultant signal to the controlling means.

40. An apparatus according to claim 39 wherein the presearching means comprises:

an input for receiving video signals from the video sensor;

a bit clock generator;

a first analog delay circuit connected to receive the video sensor input, said delay circuit causing a delay of time length equal to one horizontal video line scan;

a first analog differential comparator which receives input signals from the first analog delay circuit and from the video sensor input, said comparator outputting a signal when the input signals differ;

a first AND gate which receives one input from the bit clock generator and a second input from the output of the first analog differential comparator, said AND gate emitting an output signal when signals occur simultaneously at both inputs;

a first counter connected to receive the output of the first AND gate, said counter accumlating a total count representing the period during which the first AND gate is outputing a pulsed signal;

a first digital comparator connected to receive the count output (A) from the first counter and to compare this accumulating count against a preset test count (B) which represents the expected horizontal width of a single alphanumeric character, said comparator outputing a signal when A is less than or equal to B;

a first D-flip flop unit connected to receive the output signal from the first digital comparator, said flip flop unit outputs a signal after it has been triggered by a first output signal from the first digital converter;

a second D-flip flop unit connected to receive the output of the first D-flip flop unit and to receive the output signals from the first digital comparater, said second D-flip flop unit being activated by the output signal from the first D-flip flop unit which occurs when the first flip flop unit is activated by the first output signal emitted from the first comparator, and then is caused to emit a signal at its output when a second consecutive signal is emitted from the first comparater;

a second counter connected to receive inputs from the bit clock generator which causes the counter to accumulate counts;

a second digital comparator connected to receive the count output (C) from the second counter, and to compare this accumulating count against a preset test count (D) which represents the expected horizontal width of the area containing all alphanumeric characters of interest, said comparator outputting a signal when C is greater than or equal to D;

a second AND gate which receives inputs from the second digital comparator and the second D-flip flop unit, said AND gate emitting an output signal when its input'"'"'s both simultaneously hold an input signal, whereby the tentative detection of a field of alphanumeric characters of interest against a clear background has been accomplished;

a second analog delay circuit connected to receive the output of the first analog delay circuit, said second circuit causing a delay of time length equal to 10 bits along a horizontal video line scan;

a second analog differential comparator connected to receive the output of the second analog delay circuit and the output of the first analog delay circuit, said second analog differential comparator outputting a signal when its input signals differ, said second differential comparator being connected to feed this output signal to the second counter and the first and second D-flip flop units whereby these respective devices are reset to restart their active functions over;

a first OR gate connected to receive the output signals from the first and second analog differential comparators, said OR gate emitting a signal when either of the signals input from said first and second comparators exist, and said output of the OR gate connected to the first counter whereby this counter is reset to the start position when a signal from the OR gate output occurs; and

a third analog delay circuit connected to receive the output video signal from said first analog delay circuit, said third delay circuit causing a delay of time length equal to one horizontal video line scan.

41. An apparatus according to claim 40 wherein the means for setting a threshold comprises:

a third counter connected to receive the output of the converting means, said counter being activated to reset its count level upon the reception of an output signal from the converting means, and said counter also disposed to receive a horizontal line scan synchronizing signal from the video sensor for reseting said counter at the beginning of each TV line scan;

a decoder connected to receive the output of the converting means and the output of the third counter, said decoder serving to pass the signal from the converting means to one of a plurality of its outputs as selected by the count setting on the counter;

a plurality of sample and hold circuits, each said circuit separately connected to receive output signals from said decoder in a manner as prescribed by the count on said third counter whereby said received signals from the decoder controls activation of the sample and hold circuits, and each said sample and hold circuit being separately connected to receive the video signal from the output of the third analog delay circuit in the converting means, whereby the analog voltage level of the video signal is stored in the preselected activated sample and hold circuit; and

an analog multiplexer connected to receive the outputs of each said sample and hold circuits, and connected to receive control signals from the means for storing the horizontal and vertical coordinates, said multiplexer outputting the video voltage level signal from the proper sample and hold circuit when directed by the received control signal from the storing means.

42. An apparatus according to claim 41 wherein the means for storing the horizontal and vertical coordinates representing the location of each possible bounded area containing alphanumeric characters comprises:

a fourth counter connected to receive the horizontal line scan synchronizing signal from the video sensor for incrementing said counter one count at the beginning of each TV line scan;

a first RAM connected to receive and store the output count of the fourth counter, and connected to receive the output signal from the second AND gate within the presearching means which, when received, causes the last stored count in said counter to be outputted to the means for locating the bounded area containing alphanumeric characters;

a fifth counter connected to receive the output of the bit clock generator for causing said counter to index counts related to the linear position on a horizontal TV scan line, and connected to receive the horizontal line scan synchronizing signal from the video sensor for reseting said counter to restart at the beginning of each horizontal TV scan line;

a subtractor connected to receive the count from said fifth counter and also connected to receive the output signal from the second AND gate within the presearching means, said subtractor causing the preset test count D to be subtracted from the count in said fifth counter upon the receipt of the output signal from the second AND gate;

a second RAM connected to receive the output count from the subtractor, said RAM storing the count which represents the horizontal position of the left edge of the bounded area countaing alphanumeric characters;

a third digital comparator connected to receive the output of the second RAM, this output being the last count (F) stored in the second RAM, and connected to receive the accumulated count of the fifth counter (E), said third comparator outputting a signal when E=F with one connection of this output back to the second RAM whereby said RAM is address incremented upon the occurrence of the output signal; and

a sixth counter connected to the output of the third digital comparator whereby said counter is indexed one count for each signal emitted by the third digital comparator, said counter also connected to receive the horizontal line scan synchronizing signal from the video sensor for reseting said counter upon receipt of this signal at the beginning of each TV line scan, and the output of said sixth counter connected to the analog multiplexer within the threshold setting means for causing the proper sample and hold circuit to be outputted through the multiplexer.

43. An apparatus according to claim 42 wherein the digitizing means comprises:

a third analog delay circuit, connected to receive the output video signal of the first analog delay circuit within the presearching means, for further delaying the input video signal for a time period equal to one horizontal video line scans; and

a third analog differential comparator with one input connected to the output of the third analog delay circuit and a second input connected to the output of the means for setting a threshold, said comparator emitting a quantized digital binary signal with a logic signal of "1" for data pertaining to possible alphanumeric characters and the logic signal of "0" for data caused by the background.

44. An apparatus according to claim 43 wherein the holding means comprises:

a third RAM connected to the output of the converting means to receive and store each bounded scene of quantized video data, said RAM also connected to the controlling means for receiving command signals;

an address encoder connected to receive counts from the bit clock generator; and

an address selector connected to receive data and command signals from the controlling means, said address selector connected to output address data to the third RAM when commanded by the controlling means.

45. An apparatus according to claim 44 wherein the controlling means comprises:

a microcomputer.