Method of fabricating semiconductor devices having a diffused region of reduced length

• US 4,567,641 A
• Filed: 09/12/1984
• Issued: 02/04/1986
• Est. Priority Date: 04/12/1982
• Status: Expired due to Fees

• Current Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Original Assignee: General Electric Company
• Inventors: Baliga, Bantval J., Gray, Peter V., Love, Robert P.
• Primary Examiner(s): NOT, DEFINED
• Application Number:
  US06/650,314
• Time in Patent Office: 510 Days
• Field of Search: 148/187, 29/571, 29/578, 29/580, 357/22 E
• US Class Current: 438/201
• CPC Class Codes: H01L 21/30608 Anisotropic liquid etching H01L21/3063 takes precedence
• CPC Class Codes: H01L 21/308 using masks H01L21/3063, H01L21/3065 take precedence
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4975 being a silicide layer, e.g. TiSi2
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7396 with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

An improved semiconductor device having a diffused region of reduced length and an improved method of fabricating such a semiconductor device are disclosed. The semiconductor device may be a MOSFET or an IGR, by way of example. In a form of the method of fabricating a MOSFET, an N⁺ SOURCE is diffused into a P BASE through a window of a diffusion mask. An anisotropic or directional etchant is applied to the N⁺ SOURCE through the same window. The etchant removes most of the N⁺ SOURCE, but allows shoulders thereof to remain intact. These shoulders, which form the completed N⁺ SOURCE regions, are of reduced length, greatly reducing the risk of turn-on of a parasitic bipolar transistor in the MOSFET. The risk of turn-on of a parasitic bipolar transistor in an IGR is similarly reduced, when the IGR is fabricated by the improved method.

Claims

1. In a method of fabricating a semiconductor device of the type wherein a mask, defining a window, is applied to a major surface of a semiconductor body, and a first region of one dopant type is formed in a second region of opposite dopant type in said body by diffusing a dopant of said one type into said body through said window, with said mask serving as a diffusion barrier, the improvement comprising:

anisotropically etching into said body through said window, with said mask serving as an etch barrier;

said etch penetrating at least substantially all the way through said first region but allowing shoulders of said first region to remain intact; and

forming a short in contact with at least a portion of said first and second regions.

2. A method of fabricating a semiconductor device in accordance with claim 1 wherein said first region and said short are doped to a high level of conductivity to establish a tunnel junction between said short and said first region.

3. A method of fabricating a semiconductor device in accordance with claim 1 wherein said short is formed in said major surface.

4. A method of fabricating a semiconductor device in accordance with claim 1 wherein said etch penetrating at least substantially all the way through said first region, establishes a cut surface through said first and second regions and said short is formed in contact with said cut surface through said first and second regions.

5. The invention according to claim 1 wherein said semiconductor body comprises a substrate with an epitaxial layer thereon.

6. The invention according to claim 5 wherein said substrate comprises a DRAIN of a MOSFET of said one dopant type.

7. The invention according to claim 5 wherein said substrate comprises a region of an insulated gate rectifier of said opposite dopant type.

8. The invention according to claim 1 wherein said mask comprises conductive refractory material and an oxide of said semiconductor body, said oxide insulating said refractory material from said body.

9. The invention according to claim 1 wherein said one dopant type comprises N-type.

10. The invention according to claim 9 wherein said semiconductor body comprises silicon.