GaAs Complementary enhancement mode junction field effect transistor structures and method of fabrication
First Claim
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1. A GaAs integrated circuit structure containing complementary enhancement junction field effect transistors (JFET) comprising:
- a semi-insulating GaAs substrate having a first main surface;
at least one n channel JFET structure formed in said first main surface of the substrate, the n channel structure comprising;
source and drain regions formed by a first ion implantation of n type impurity ions into two regions of the substrate separated by an intermediate region;
a channel region formed by exposing a portion of the intermediate region to a second ion implantation of further n type impurity ions, the second implantation also implanting into the source and drain regions; and
a gate region formed by exposing a portion of the channel region to a third ion implantation of p type impurity ions;
said source, drain and gate regions having electrical contacts emplaced atop them; and
at least one p channel JFET structure formed in said first main surface of the substrate, the p channel structure comprising;
a p channel region formed by a channel ion implantation of p type impurity ions into the substrate;
source and drain regions formed by ion implantation of p type impurity ions into respective spaced-apart areas of the p channel region, the remainder of the p channel region being protected from this ion implantation; and
a gate region formed by exposing a portion of the channel region intermediate the source and drain regions to an ion implantation of n type impurity ions;
said source, drain and gate regions having electrical contacts emplaced atop them.
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Abstract
Ultra low-power GaAs complementary junction field effect transistors are implemented in the design of complementary integrated circuits using a planar technology in conjunction with multiple and selective ion implantation. Both junction FETs, namely the p and n channel devices, are enhancement mode devices and biased in the forward direction thus leading to the advantageous DCFL (directly coupled field effect transistor logic) with one power supply, low power dissipation and high packing densities, all prerequisites for VLSI (very large scale integration).
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4 Claims
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1. A GaAs integrated circuit structure containing complementary enhancement junction field effect transistors (JFET) comprising:
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a semi-insulating GaAs substrate having a first main surface; at least one n channel JFET structure formed in said first main surface of the substrate, the n channel structure comprising; source and drain regions formed by a first ion implantation of n type impurity ions into two regions of the substrate separated by an intermediate region; a channel region formed by exposing a portion of the intermediate region to a second ion implantation of further n type impurity ions, the second implantation also implanting into the source and drain regions; and a gate region formed by exposing a portion of the channel region to a third ion implantation of p type impurity ions;
said source, drain and gate regions having electrical contacts emplaced atop them; andat least one p channel JFET structure formed in said first main surface of the substrate, the p channel structure comprising; a p channel region formed by a channel ion implantation of p type impurity ions into the substrate; source and drain regions formed by ion implantation of p type impurity ions into respective spaced-apart areas of the p channel region, the remainder of the p channel region being protected from this ion implantation; and a gate region formed by exposing a portion of the channel region intermediate the source and drain regions to an ion implantation of n type impurity ions;
said source, drain and gate regions having electrical contacts emplaced atop them. - View Dependent Claims (2, 3, 4)
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Specification