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Inversion-mode insulated-gate gallium arsenide field-effect transistors

  • US 4,568,958 A
  • Filed: 01/03/1984
  • Issued: 02/04/1986
  • Est. Priority Date: 01/03/1984
  • Status: Expired due to Fees
First Claim
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1. An inversion-mode insulated-gate field-effect transistor comprising:

  • source and drain regions of one conductivity type separated by a shield base region of the opposite conductivity type;

    said shield base region including a channel layer extending between said source and drain regions;

    a gate electrode insulatively spaced from said channel layer and configured for inducing in said channel layer, when gate voltage is applied thereto, an inversion channel region conductively coupling said source and drain regions;

    at least a portion of said drain region comprising gallium arsenide semiconductor material; and

    at least a channel-supporting portion of said shield base region comprising a semiconductor material other than gallium arsenide and within which inversion regions may readily be formed, said channel layer being included in said channel-supporting portion.

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