Video sound and system control circuit

• US 4,569,019 A
• Filed: 06/03/1983
• Issued: 02/04/1986
• Est. Priority Date: 06/03/1983
• Status: Expired due to Term

• Current Assignee: AD Technologies LLC
• Original Assignee: Commodore Business Machines, Inc
• Inventors: DiOrio, David W., Ahrens, Bruce F., Raible, Robert J., Yang, Chaoynan E.
• Primary Examiner(s): Harkcom, Gary V.
• Application Number:
  US06/500,996
• Time in Patent Office: 977 Days
• Field of Search: 364/400, 364/410, 364/513.5, 364/200 MS File, 364/900 MS File, 364/521, 273/DIG. 28, 358/903, 381/51, 381/53, 340/720, 340/723, 340/732
• US Class Current: 463/31
• CPC Class Codes: A63F 13/00 Video games, i.e. games using an electronically generated display having two or more dimensions gaming systems which provide a financial reward G07F17/32
• CPC Class Codes: A63F 13/23 for interfacing with the game device, e.g. specific interfaces between game controller and console

Abstract

Programmable I/O (input/output) interface circuitry provides video and audio signals, needed for a video computer/game, to a commercial color television type display/monitor and may be implemented in HMOS, (H type metal oxide semiconductor) large-scale-integrated circuitry. The system architecture allows for reduced chip count, and improved reliability while providing adequate synchronization pulses, luminance level signals, chrominance phase shift signals, raster control and cursor control video and three independently controlled audio voices. A software selectable keyboard latch input, plural speed processing for faster operation when outside the active display area or during blanking, all system control signals necessary for system operation and 3 independently controlled interrupt generating timers are also provided.

Claims

1. A programmable audio and video display driver circuit, as connected to a video game/home computer, is capable of driving a color television type audio/video display, independently of the video game/home computer main circuitry, comprising:

a bus architecture for transfering data and instructions;

a microprocessor connected to said bus architecture;

at least one read-only memory (ROM) connected to said bus architecture and able to receive address instructions and supply data thereto;

at least one dynamic random access memory (RAM) connected to said bus architecture and able to receive and supply data and instructions thereto;

at least one Schottky-type driver circuit connected to drive said random access memory under address instructions from said microprocessor through said bus architecture connection;

keyboard means;

a joy stick input connected to said microprocessor;

a source of software instructions connected to input a program to said microprocessor; and

an interface circuit connected to said bus architecture to receive and send data and instructions from said microprocessor and connected to said keyboard means, said interface circuit being connected to supply signals to each said Schottky driver and to each said RAM and to receive signals from each said RAM, said interface circuit providing audio and video display signals usuable by said color television type display and wherein interface circuit contains therein a two-speed clock and a three oscillator voice generator.

2. The display driver circuit of claim 1 wherein said microprocessor is an 8 bit word microprocessor;

wherein said at least one ROM is a pair of 16K, 8 bit word, ROMs each connected to said bus architecture;

wherein said at least one RAM is a pair of RAMs each connected to said bus architecture; and

wherein said at least one Schottky-type driver circuit is a pair of Schottky-type driver circuits, connected to a first one of said pair of RAMs.

3. The display driver circuit of claim 2 wherein said keyboard means includes a keyboard having a decoder, said keyboard decoder output being connected to said interface circuit;

wherein said second of said pair of RAMs is connected in series with said first RAM of said pair;

wherein said second of said pair of ROMs is connected in series with said first ROM of said pair;

wherein each of said pair of Schottky-type driver circuits is connected to said interface circuit;

wherein said microprocessor is programmable having a software input;

wherein each of said pair of RAMs is connected to said interface circuit; and

wherein said interface circuit includes commercial television type audio and video signal outputs.

4. The display driver circuit of claim 3 wherein said interface circuit includes:

a data port connectable to said bus architecture;

an address port connectable to said bus architecture;

a keyboard port connectable to said bus architecture;

a data transmissions line connected to said data port and said keyboard port;

an address transmission line connected to said keyboard port;

a control signal transmission line connected to said address port;

a plurality of operation registers connected to said address transmission line;

a random access memory (RAM) connected to said data transmission line, said control signal transmission line and said plurality of operation registers;

a sound generator connected to said plurality of operation registers;

a television video synchronous luminance (SYNC-LUM) and chrominance (CHROM) signal generator connected to said data transmission line and said control signal transmission line;

a NTSC/PAL selectable signal controller connected to said control signal transmission line; and

a chip timing control circuit connected to each of said RAM, plurality of operation register, said sound generator and said SYNC-LUM and CHROM generator.

5. A programmable interface controller circuit for an audio and video display driver circuit, which is to provide audio and video information to a commercial television type display, to display video game/home computer information, said driver circuit being connected as part of a video game/home computer and having as a portion thereof, apart from said computer'"'"'s arithmetic microprocessor and other circuitry, its own microprocessor, memory, information buses, user input and software input, comprising:

means, connected to said driver circuit microprocessor and memory, for programmably setting a voice, said voice being a mix of three different frequency generators as a part thereof, two of which providing square wave signals and the third being selectable between a square wave and white noise;

means, connected to said voice setting means, for generating video color character and high resolution color graphics display signals according to program instructions received;

means, connected to said driver cirucit information buses and memory, for providing control if said information buses and said memory; and

input/output connections means for connecting said voice setting means and said video color character and graphics generating means to a commercial television type display.

6. The programmable interface controller circuit for the audio and video display driver circuit of claim 5 wherein said programmably setting voice means includes:

a plurality of sound instruction word reload registers, a voice instructions word reload register, a plurality of sound active instruction word registers and a noise active instruction word register comprising a sound section register array, said sound section register array being loadable from a bus connection;

an audio address decoder connected to said sound section register array and being addressable from a bus connection;

a voice register being loadable from a bus connection; and

an audio mixer connected to said sound section register array and said voice register, said mixer including said two square wave generators and said selectable square wave/white noise generator.

7. The programmable interface controller circuit for the audio and video display driver circuit of claim 6 wherein said video color character and color graphics signals generating means includes:

a clock;

a plurality of timers connected to said clock;

a first multiplex circuit connected to said plurality of timers;

a horizontal dot counter connected to said first multiplex circuit;

a horizontal address decoder addressable from a bus connection;

a horizontal register connected to said horizontal dot counter and said horizontal address decoder;

a plurality of registers forming a video section register for refresh word, master word, cursor word, comparator word, video matrix word, video matrix reload word and vertical line word;

a vertical address decoder addressable from a bus connection and connected to said video section register array;

a first address decoder addressable from a bus connection;

a vertical blink register loadable from a bus connection and connected to said first address decoder;

a vertical register 3 bit counter connected to said first address decoder and said vertical blink register;

a second multiplex circuit connected to said video section register array, to said vertical blink register, to said vertical register 3 bit counter and to said sound section register array;

a horizontal display decoder connected to said horizontal register;

a vertical line counter connected to said second multiplex circuit and said horizontal display decoder;

a vertical line driver connected to said vertical line counter;

a vertical display decoder connected to said vertical line decoder; and

video horizontal and vertical generator means including vertical scroll and horizontal scroll control circuit means and color selection means connected to said horizontal display decoder and to said vertical display decoder.