Image data masking apparatus

• US 4,569,079 A
• Filed: 03/03/1983
• Issued: 02/04/1986
• Est. Priority Date: 03/11/1982
• Status: Expired due to Fees

• Current Assignee: Hajime Industries Limited
• Original Assignee: Hajime Industries Limited
• Inventors: Yoshida, Hajime
• Primary Examiner(s): Boudreau, Leo H.
• Application Number:
  US06/471,715
• Time in Patent Office: 1,069 Days
• Field of Search: 382/1, 382/41, 382/44, 382/45, 382/48, 382/61, 382/69, 358/22, 358/33, 358/165, 358/183, 358/160, 364/518
• US Class Current: 382/283
• CPC Class Codes: H04N 23/81 for suppressing or minimising disturbance in the image signal generation

Abstract

The target screen of a television camera is divided into a matrix in horizontal and vertical directions to receive image data signals as divided in the matrix for subsequent processing. A memory circuit having the same number of memory elements as the divisions of the matrix, a circuit for scanning addresses of the memory elements of the memory circuit in synchronization with scanning in the television camera, a circuit for preliminarily memorizing signals, which are used to discriminate which of the image data signals are processed or not, on memory elements of the memory circuit with addresses corresponding to the image data signals respectively and a circuit for generating a control signal based on the memory data signal from the memory circuit to determine which image data signals is used or not in response to scanning of the target screen of the television camera is provided. A circuit for controlling supply of the image data signal from the television camera to the processing apparatus is also provided.

Claims

1. An image data masking apparatus for use with image data processing apparatus comprising:

a television camera including a target screen formed of a number of sensor elements arranged in a matrix in horizontal and vertical directions, said sensors being adapted to pick up an object from said television camera and producing an image data signal of said object;

a processor for processing the image data signal from said television camera;

a memory circuit having a plurality of memory elements the number of which being equal to the number of said sensor elements and which are arranged in a matrix similar to that of said sensor elements, for storing the image data from said television camera, each of said memory elements having a specific address corresponding to a specific one of said sensors;

scanning means for scanning the addresses of said memory elements and relaying both the horizontal and vertical synchronizing signals of said television camera in synchronization with the scanning of said sensor elements by said television camera so as to store image data from respective sensor elements on corresponding memory elements;

means for producing signals, indicative of said sensors from which of said image data from said television camera are to be masked, and for storing said signals in memory elements of said memory circuit at corresponding addresses;

means for generating a control signal for read out of said memory elements from said memory circuit signals in direct response to the scanning of said target screen to indicate which portion of said image data is to be processed;

and means for controlling the supply of the image data from the television camera to said processor in response to said control signal.

2. The image data masking apparatus according to claim 1, wherein said scanning means comprises a horizontal synchronizing signal separating circuit for separating a horizontal synchronizing signal from the image data signal applied thereto from said television camera and a first binary counter supplied with the horizontal synchronizing signal thus separated as its clock and producing output signals which are applied to said memory circuit at its higher addresses to designate addresses of said memory elements in the vertical direction.

3. The image data masking apparatus according to claim 2 wherein said scanning means includes a clock generator for producing clock pulses, the number of which is same as the number of said sensor elements in the horizontal direction and a second binary counter supplied with the clock pulses and producing output signals which are applied to said memory circuit at its lower addresses to designate addresses of said memory elements in the horizontal direction.

6. The image data masking apparatus according to claim 2 wherein said scanning means includes a vertical synchronizing signal separating circuit for separating a vertical synchronizing signal from said image data signal and a first inverter for inverting the vertical synchronizing signal applied thereto from said vertical synchronizing signal separating circuit in polarity, said inverted vertical synchronizing signal being supplied to said first binary counter at its clear input terminal.

7. The image data masking apparatus according to claim 1, herein memorizing means comprises switch means for controlling writing and reading of said memory circuit.

8. The image data masking apparatus according to claim 1, wherein said control signal generating means comprises an inverter for inverting the control signal in polarity.

9. The image data masking apparatus according to claim 1, wherein said supply controlling means is a digital switch.

10. The image data masking apparatus according to claim 1, wherein said supply controlling means is an analog switch.

11. The image data masking apparatus according to claim 1 including a comparator which receives the image data signal from said television camera and converts said image data signal to binary data, said binary data being supplied to said memory circuit.

4. The image data masking apparatus according to 3 wherein said scanning means includes a horizontal synchronizing signal separating circuit for separating a horizontal synchronizing signal from said image data signal and a second inverter for inverting the horizontal synchronizing signal applied thereto from said horizontal synchronizing separating circuit in polarity, an inverted horizontal synchronizing signal being applied to said second binary counter at its clear input terminal.

5. The image data masking apparatus according to claim 4, including an OR gate through which the inverted horizontal and vertical synchronizing signals from said second and first inverters and supplied to said clock generator at its enable input terminal.