Video signal processing device including emphasis and/or de-emphasis circuit

• US 4,570,193 A
• Filed: 05/04/1982
• Issued: 02/11/1986
• Est. Priority Date: 05/08/1981
• Status: Expired due to Term

• Current Assignee: Canon Ayutthaya Limited (Canon Inc.)
• Original Assignee: Canon Ayutthaya Limited (Canon Inc.)
• Inventors: Yamashita, Shinichi
• Primary Examiner(s): Richardson, Robert L.
• Application Number:
  US06/374,881
• Time in Patent Office: 1,379 Days
• Field of Search: 358/335, 358/166, 358/167, 358/162, 358/340, 333/28 R, 333/28 T, 333/165-166, 360/65, 360/33.1, 360/30, 455/43, 455/63
• US Class Current: 386/269
• CPC Class Codes: H04N 5/923 using preemphasis of the signal before modulation and deemphasis of the signal after demodulation volume compression or expansion in amplifiers in general H03G7/00

Abstract

A video signal processing device including emphasis and/or de-emphasis circuit being arranged to have a circuit to emphasize a high frequency component of a video signal which has been introduced at a time of frequency modulation in a linear phase. Further, the circuit clips an output of the emphasis circuit with a prescribed amplitude and at the same time supplies a frequency modulated video signal to a de-emphasis circuit which has a characteristic of being contrary to the frequency characteristic of the emphasis circuit.

Claims

1. A video signal processing device including a de-emphasis circuit, comprising:

(a) a de-emphasis circuit to de-emphasize high frequency components of a de-modulated video signal, said de-emphasis circuit including a transversal filter of a low pass type which includes analog delay elements and a coefficient imparter to impart weight to each tap output of said delay elements; and

(b) a noise clipping circuit to eliminate noise components of large amplitude out of output signals of said de-emphasis circuit, said noise clipping circuit including a first subtracting circuit to obtain a difference between one of the delay outputs of each tap of said delay elements and an output of the de-emphasis circuit.

2. A device according to claim 1, wherein said noise clipping circuit further includes an amplitude limiter which limits an amplitude of an output of said first subtraction circuit.

3. A device according to claim 2, wherein said noise clipping circuit further contains a second subtraction circuit which obtains a difference between an output of said amplitude limiter and an output of the de-emphasis circuit.

4. A device according to claim 1, wherein the delay output supplied to the first subtraction circuit is the output from a center tap out of the delay elements.

5. A video signal processing device comprising:

(a) an emphasis circuit including;

a group of delay elements connected in series, to which a video signal which has been introduced to the emphasis circuit is supplied;

a group of coefficient imparters for imparting weight to each tap output of the delay elements; and

an operation circuit which operates outputs of the coefficient imparters to generate a single output, the delay time of each of said group of delay elements and the coefficient of each of said group of coefficient imparters being determined in such a manner that the output signal of the operation circuit represents the video signal introduced to said emphasis circuit and emphasized on the high frequency component in a linear phase; and

(b) a clipping circuit for clipping an output signal of said emphasis circuit with a predetermined amplitude.

6. A device according to claim 5, wherein said group of delay elements is formed by a charge transfer device.

7. A device according to claim 5, further comprising a de-emphasis circuit including:

a group of delay elements connected in series and supplied with a video signal introduced to the de-emphasis circuit;

a group of coefficient imparters for imparting weight to each tap output of said group of delay elements; and

an operation circuit for operating outputs of said group of coefficient imparters to generate a single output, the delay time of each of said group of delay elements and the coefficient of each said group of coefficient imparters being determined in such a manner that the output signal of the operation circuit represents the video signal introduced to said de-emphasis circuit and de-emphasized on the high frequency component in a linear phase.