CMOS Circuit with reduced power dissipation and a digital data processor using the same

• US 4,570,219 A
• Filed: 10/29/1982
• Issued: 02/11/1986
• Est. Priority Date: 11/11/1981
• Status: Expired due to Term

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Nakamura, Hideo, Matsubara, Kiyoshi, Shibukawa, Masaru
• Primary Examiner(s): NOT, DEFINED
• Assistant Examiner(s): Munteanu, Florin
• Application Number:
  US06/437,674
• Time in Patent Office: 1,201 Days
• Field of Search: 307/540, 307/542, 307/544, 307/555, 307/557, 307/450-453, 307/481, 307/605, 307/606, 364/200 MS File, 364/900 MS File, 364/707
• US Class Current: 713/401
• CPC Class Codes: G06F 1/3228 Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
• CPC Class Codes: G06F 9/226 Microinstruction function, e.g. input/output microinstruction; diagnostic microinstruction; microinstruction format
• CPC Class Codes: G06F 9/30083 Power or thermal control instructions
• CPC Class Codes: H03K 19/0963 using transistors of complementary type H03K19/0966 takes precedence

Abstract

In an information processor employing a CMOS circuit comprising a first inverter constructed of CMOS field effect transistors and performing a dynamic operation in response to clock signals, and a second inverter which receives an output from the first inverter and which is also constructed of CMOS field effect transistors, the supply of clock signals to the first inverter is stopped in response to a particular microinstruction. After the supply of clock signals is stopped, the output voltage of the first inverter is clamped to a predetermined value, thus reducing the power dissipation in the dynamic CMOS circuit and also preventing the deterioration of data during the stopping of clock signals.Y

Claims

1. An information processor wherein respective machine instructions are executed in microinstruction sequences in synchronism with clock signals;

said information processor comprising;

a memory which stores said microinstruction sequences therein;

a control register which serves to hold the microinstructions fetched from said memory;

processing means including an arithmetic logic unit for processing data;

means for supplying said processing means with the microinstructions held in said control register including a delay circuit which serves to afford unequal delay times to respective parts of the microinstruction supplied from said control register;

a generator for the clock signals;

a generator circuit for supplying an interrupt signal;

a first circuit which normally supplies the clock signals to the interrupt signal generator circuit; and

a second circuit which controls the supply of the clock signals to said memory, said control register and said arithmetic logic unit;

said delay circuit including a plurality of inverter trains in which unequal numbers of inverter stages for affording the unequal delay times are connected in series, said inverter trains including inverters which perform dynamic operations in response to the clock signals, said second circuit including means for stopping the supply of the clock signals in response to a specific microinstruction within a microinstruction sequence for a predetermined specific machine instruction when said specific microinstruction has been loaded in said control register and for restarting the supply of the clock signals in response to supply of the interrupt signal by said interrupt signal generator circuit.

2. An information processor according to claim 1, wherein said second circuit includes clamp means for clamping ouput voltages of the dynamic inverters at a predetermined value during the time the supply of the clock signals is stopped.

3. An information processor according to claim 2, wherein said clamp means clamps an output voltage of that one of said dynamic inverters whose output is applied to an inverter performing a static operation.

4. An information processor according to claim 3, wherein said inverter performing the static operation is an inverter which performs the static operation during the time the supply of the clock signals is stopped and which performs the dynamic operation during the time of supply of the clock signals.

5. An information processor according to claim 2, wherein said predetermined value is so determined that, at the time at which signals responsive to the clamped predetermined value are delivered to output ends of said inverter trains after the supply of the clock signals has been restarted, said signals do not become any signal which starts said arithmetic logic unit.