High speed parallel bus and data transfer method

• US 4,570,220 A
• Filed: 11/25/1983
• Issued: 02/11/1986
• Est. Priority Date: 11/25/1983
• Status: Expired due to Fees

• Current Assignee: Radisys Corporation (Reliance Industries Limited)
• Original Assignee: Intel Corporation
• Inventors: Farrell, Robert L., Tetrick, Raymond S., Sarabi, Alireza, Jacks, Edwin L. Jr., Kassel, Steven D., Beaston, John, Balachandran, Sudarshan
• Primary Examiner(s): NOT, DEFINED
• Application Number:
  US06/555,027
• Time in Patent Office: 809 Days
• Field of Search: 364/200 MS File
• US Class Current: 710/306
• CPC Class Codes: G06F 13/374 using a self-select method with individual priority code comparator
• CPC Class Codes: G06F 13/376 using a contention resolving method, e.g. collision detection, collision avoidance
• CPC Class Codes: G06F 13/4217 with synchronous protocol
• CPC Class Codes: G06F 13/4239 with asynchronous protocol
• CPC Class Codes: G06F 13/4243 with synchronous protocol

Abstract

A multiple bus system architecture and improved data transfer methods are disclosed for transferring data between a plurality of data processing resources. The bus structure of the present invention includes both a parallel and serial bus which interconnects data processing units and peripheral devices (collectively referred to as "agents") to permit the exchange of data and messages at high speed using a minimum of "handshake" events prior to the actual data transfer. Both the serial and parallel bus protocals are controlled by message control means coupled to each communicating agent. A local bus is coupled to processing agents within the system such that local memory and secondary processing resources may be accessed without impacting data traffic along the parallel bus. Direct access to resources coupled to the local bus of an agent from other bus agents is also controlled by the message control means.

Claims

1. A high speed parallel bus structure for transferring data between a plurality of data processing devices ("agents"), comprising:

address data lines for transmitting address and data information between said agents;

command lines for transmitting commands from a requesting agent to a replying agent, such that said requesting agent may transmit a requester ready (REQ RDY) signal to said replying agent notifying said replying agent that said requestor is ready to proceed with the data operation identified by said command, and a replier ready signal (REPLY RDY) transmitted by said replying agent on said command lines notifying said requesting agent that said replying agent is prepared to proceed with said data operation;

said command lines being reallocated between said requesting and replying agents once said command has been transmitted, thereby permitting the transmission of said REQ RDY and REPLY RDY signals;

said data to be transferred being considered valid only upon the assertion of both said REQ RDY and REPLY RDY signals;

message control means coupled to each of said agents in said bus structure for coupling said agents to said parallel bus;

said message control means further including arbitration means for allocating the use of said parallel bus between agents;

whereby data is transferred between agents at high speed.

2. The parallel bus structure as defined by claim 1, wherein said message control means for each agent further includes means for generating an end-of-cycle (EOC) signal generally concurrent with said REQ RDY signal, in the event no further data transfers between said requesting and replying agents are to take place beyond the current transfer cycle.

3. The parallel bus structure as defined by claim 2, wherein said arbitration means includes bus request (BREQ) signal generation means for generating a BREQ signal and asserting said parallel bus.

4. The parallel bus structure as defined by claim 1, wherein said arbitration means includes arbitration code generation means for transmitting a digital code corresponding to a unique arbitration number for each agent on arbitration lines, each arbitration number denoting a relative priority for access to said parallel bus.

5. The parallel bus structure as defined by claim 4, further including service module means coupled to said bus for providing each of said agents with said particular digital arbitration code when said bus is powered-up.

6. The bus structure as defined by claim 4, wherein said arbitration means includes high priority signal generation means for transmitting a high priority signal on a high priority line coupled to each agent on said parallel bus, such that an agent asserting said high priority signal will gain access to said parallel bus irrespective of said particular agent'"'"'s arbitration number priority.

7. The bus structure as defined by claim 6, wherein a requesting agent asserts the address of a replying agent on said address/data lines substantially concurrently with the assertion of a command to said replying agent on said command lines.

8. The bus structure as defined by claim 1, wherein data is asserted on said address/data lines once said replying agent has received said command on said command lines and said command lines are reallocated.

9. The bus structure as defined by claim 7, wherein said replying agent includes exception signal generating means for transmitting an exception signal to said requesting agent on exception lines coupled to each agent in the event of a data transfer error, such that said data transfer cycle is aborted.

10. The bus structure as defined by claim 8, wherein a primary processor of said requesting agent generates a message request and passes said request to said message control means of said requesting agent, which encapsulates said request for transmission on said parallel bus.

11. The bus structure as defined by claim 9, wherein said encapsulation includes the addition of a first liason number identifying the particular message request.

12. The bus structure as defined by claim 10, wherein said encapsulated request is received by said message control means of said replying agent and transmitted along an internal bus to a processor of said replying agent.

13. The bus structure as defined by claim 10, wherein said replying agent'"'"'s processor transmits a response to said received message request, and passes said response to said message control means for said replying agent which encapsulates said response and includes the addition of a second liason number identifying the particular response.

14. A method for transferring data in a multiple bus structure between a plurality of data processing devices ("agents") including a requesting agent and replying agent on a parallel bus, comprising the steps of:

transmitting a command on command lines coupled to each of said agents from said requesting agent to said replying agent;

transmitting address information on address/data lines coupled to each of said agents from said requesting agent to said replying agent;

applying a requestor ready (REQ RDY) signal transmitted by said requesting agent on first selected command lines;

applying a replier ready (REPLY RDY) signal transmitted by said replying agent on second selected command lines;

applying data to said address/data lines, said data being considered valid only upon the application of both the REQ RDY and REPLY RDY signals;

deasserting said REQ RDY and REPLY RDY signals once said data is latched off of said address/data lines;

whereby data is transferred between said agents at high speed.

15. The method as defined by claim 14, wherein additional data may be transferred between said requesting and replying agents upon the application of new data to said address/data lines and the re-application of said REQ RDY and REPLY RDY signals.

16. The method as defined by claim 15, wherein said requesting agent generates an end-of-cycle (EOC) signal and applies said signal to selected command lines generally concurrently with said REQ RDY signal in the event that no further data transfers between said requesting and replying agents are to take place.

17. The method as defined by claim 16, further including the step of arbitrating the access to said parallel bus between agents.

18. The method as defined by claim 17, wherein said arbitration step includes generating a bus request (BUS REQ) signal by a requesting agent and applying said BUS REQ signal to a bus request line coupled to each agent on said parallel bus.

19. The method as defined by claim 18, wherein said arbitration step further includes the application by a requesting agent of a digital code corresponding to a unique arbitration number on an arbitration bus, said arbitration number denoting a relative priority for access to said parallel bus.

20. The method as defined by claim 19, wherein a requesting agent may gain access to said parallel bus irrespective of said arbitration number priority by asserting a high priority signal on a high priority line coupled to each of said agents.

21. The method as defined by claim 20, wherein said replying agent generates an exception signal and applies said exception signal to exception lines coupled to said agents in the event of a data transfer error, such that said data transfer cycle is aborted.