Dynamic random-access memory

• US 4,570,242 A
• Filed: 10/27/1982
• Issued: 02/11/1986
• Est. Priority Date: 10/27/1981
• Status: Expired due to Term

• Current Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Original Assignee: Nippon Electric Company Limited (NEC Corporation)
• Inventors: Nagami, Akira
• Primary Examiner(s): Popek, Joseph A.
• Application Number:
  US06/436,991
• Time in Patent Office: 1,203 Days
• Field of Search: 365/222, 365/182
• US Class Current: 365/222
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles

Abstract

A dynamic memory is capable of performing an internal charge storing refreshing operation with a low power consumption. The memory comprises an inverter for receiving a signal from the outside. The inverter is composed of an input transistor and a load circuit whose ability to feed a current to the input transistor is controllable and is made smaller during the internal refresh operation.

Claims

1. A dynamic memory comprising a memory array of memory cells arranged in rows and columns, row address means for receiving a set of row address signals, first means for receiving a refresh control signal having first and second logic levels, a refresh address counter for operatively designating a row address to be refreshed in response to said first level of said refresh control signal, row decoding means coupled to said row address means and to said refresh address counter for operatively selecting one of said rows to refresh the memory cells coupled to the selected row, said row decoding means being adapted to take in the contents of said refresh address counter in response to said first level of said refresh control signal and take in the row address signals received by said receiving means in response to said second level of said refresh control signal, said first means including first and second series circuits of an input switching means and a load circuit, the input switching means of said first series circuit receiving said refresh control signal, the input switching means of said second series circuit receiving an output of said first series circuit, the input switching means of one of said first and second series circuits assuming a conductive state in response to said first level of said refresh control signal to cause a current flow through the load circuit, and a current control circuit for operatively decreasing an amount of current flowing through said load circuit of at least said one of said first and second series circuits in response to said first level of said refresh control signal.

2. The memory device according to claim 1, in which said load circuit of at least said one of said first and second series circuits includes a first field effect transistor, means for continuously biasing said first transistor into a conductive state and a second field effect transistor connected in parallel with said first transistor and having a smaller resistance than said first transistor, said second transistor being adapted to assume conductive and non-conductive states in response to said second and first levels of said refresh control signal, respectively.

3. The memory device according to claim 1, further comprising means for receiving a chip enable signal, and clock generating means for generating a clock signal for controlling operation of said memory array, said clock generating means includes a series circuit comprising first and second transistors coupled between a reference potential and an output node, said first transistor assuming a conductive state when said chip enable signal is at an inactive state, said second transistor assuming a conductive state when said refresh control signal is at said first level, first and second load transistors coupled between said output node and a power voltage, means for continuously placing said first load transistor in a conductive state, and means for placing said second load transistor in a conductive state when said refresh control signal assumes said first level.

4. A dynamic memory comprising an array of dynamic memory cells arranged in rows and columns, a first terminal for receiving a refresh control signal having first and second logic levels, address input means for receiving a set of address signals, an internal address generating circuit for operatively generating refresh address information, a second terminal for receiving a chip enable signal having third and fourth logic levels, an internal clock signal generator coupled to said first and second terminals for operatively generating a series of clock signals, a refresh circuit coupled to said array, said refresh circuit being responsive to said clock signals to refresh the memory cells of the selected row by said set of address signals when said refresh control signal is at said first logic level and said chip enable signal is at said third logic level and refreshing the memory cells of the designated row by said refresh address information when said refresh control signal is at said second logic level and said chip enable signal is at said fourth logic level, said internal clock signal generator generating said series of clock signals at a first cycle time when said refresh control signal is at said first logic level and said chip enable signal is at said third logic level and at a second cycle time when said refresh control signal is at said second logic level and said chip enable signal is at said fourth logic level, said second cycle time being longer than said first cycle.

5. The memory according to claim 4, in which said clock signal generator including a first series circuit of a first input transistor and a load circuit, said load circuit having first and second load transistors connected in parallel, said first input transistor receiving said refresh control signal, means for continuously placing said first load transistor in a conductive state, and a control means for operatively making said second load transistor conductive when said refresh control signal is at said first logic level.

6. The memory according to claim 5, in which a resistance of said first load transistor is larger than the resistance of said second transistor.

7. A semiconductor circuit comprising:

a first field-effect transistor having a drain-source current path coupled between a first power terminal and a first node and having a gate connected to a second node;

means for continuously placing said first transistor in a conductive state;

a first capacitor having a first terminal connected to said second node and a second terminal connected to said first node;

a second field effect transistor having its drain-source current path coupled between said first node and a second power terminal and having a gate for receiving a first signal;

a third field effect transistor with its drain-source current path coupled between said first power terminal and said first node and having a gate connected to a third node;

a fourth field effect transistor with its drain-source current path coupled between a fourth node for receiving a second signal and said third node and having a gate connected to said first power terminal; and

a second capacitor having a first terminal connected to said third node and a second terminal connected to said first node, said second signal being maintained at an active level during normal operations and said first node being driven by said first and third transistors in order to generate with a relatively high speed an output signal having an opposite-phase as compared to the phase of said first signal at said first node while in a power down mode, said second signal being maintained at an inactive level, and said third transistor being made non-conductive in order to drive said first node by means of said first transistor, thereby enabling said opposite-phase output signal to be generated with a relatively slow speed at said first node.

8. The circuit according to claim 7, in which a resistance of said first transistor is larger than the resistance of said third transistor.

9. A semiconductor circuit comprising a logic section including at least one logic input transistor, a first load circuit connected in series with said logic section, a second load circuit connected in series with said logic section and in parallel with said first load circuit, means for supplying a first logic signal to said logic input transistor, control means responsive to a second logic signal for enabling said second load circuit, and means for continuously enabling said first load circuit, wherein an amount of a current flowing to said logic section is controlled between two different values in response to said second logic signal.

10. The semiconductor circuit according to claim 9, in which said second logic signal is independent of said first logic signal.

11. The semiconductor circuit according to claim 9, in which said second logic signal is derived from said first logic signal.

12. The semiconductor circuit according to claim 9, in which said second load circuit includes a first transistor coupled between a power voltage terminal and said logic section, and a second transistor coupled between the gate of said first transistor and a first node to which said second logic signal is applied.

13. A semiconductor circuit comprising means for receiving a control signal, a series circuit of a logic section and load section, an output terminal coupled to the intermediate junction of said series circuit, said logic section having an input transistor for receiving a logic signal, said load section including a control terminal for changing between first and second values an amount of current flowing therethrough, and means coupled to said control terminal for controlling said load section in response to said control signal.

14. The semiconductor circuit according to claim 13, in which said load section includes first and second load transistors connected in parallel, a third transistor coupled between the gate of said second load transistor and said control terminal, and means for placing said first load transistor in a conductive state.

15. A semiconductor circuit comprising a switching means responsive to an input signal for attaining a switching operation, a first load having a first resistance, means for permanently connecting said first load to said switching means, a second load having a second resistance, and control means coupled to said second load for connecting said second load to said switching means during a first period of time when the switching operation of said switching means is done two or more times and for disconnecting said second load from said switching means during a second period of time which is different from said first period of time.

16. The semiconductor circuit according to claim 15, in which said first resistance is higher than said second resistance.

17. A method for retaining data stored in a dynamic memory provided with a clock generator, said method comprising the steps of:

(a) setting said memory in an access mode to cause a first amount of current through at least two parallel connected load means for generating clock signals at a relatively high speed;

(b) performing read or write operations for the memory cells selected by address input signals in response to said clock signals generated at a relatively high speed;

(c) setting said memory in self-refresh mode to cause a second amount of current through only one of said load means for generating clock signals at a relatively slow speed, said second amount of current being less than said first amount of current; and

(d) refreshing the memory cells sequentially in response to said clock signals generated at a relatively slow speed.