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Dynamic random-access memory

  • US 4,570,242 A
  • Filed: 10/27/1982
  • Issued: 02/11/1986
  • Est. Priority Date: 10/27/1981
  • Status: Expired due to Term
First Claim
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1. A dynamic memory comprising a memory array of memory cells arranged in rows and columns, row address means for receiving a set of row address signals, first means for receiving a refresh control signal having first and second logic levels, a refresh address counter for operatively designating a row address to be refreshed in response to said first level of said refresh control signal, row decoding means coupled to said row address means and to said refresh address counter for operatively selecting one of said rows to refresh the memory cells coupled to the selected row, said row decoding means being adapted to take in the contents of said refresh address counter in response to said first level of said refresh control signal and take in the row address signals received by said receiving means in response to said second level of said refresh control signal, said first means including first and second series circuits of an input switching means and a load circuit, the input switching means of said first series circuit receiving said refresh control signal, the input switching means of said second series circuit receiving an output of said first series circuit, the input switching means of one of said first and second series circuits assuming a conductive state in response to said first level of said refresh control signal to cause a current flow through the load circuit, and a current control circuit for operatively decreasing an amount of current flowing through said load circuit of at least said one of said first and second series circuits in response to said first level of said refresh control signal.

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