Randomized-clock circuit
First Claim
1. A randomized-clock circuit comprising a maximal length pseudorandom sequence generator (MLPSG), a periodic circuit clock, a multiplier, a circuit to start a pseudorandom sequence and a pulse width and amplitude adjusting circuit, the multiplier, multiplying the output of the MLPSG with the output of the periodic circuit clock, is providing at its output a random pulse train of known sequence length and gap statistics with truncated exponential distribution, the MLPSG comprises an N-stage shift register, selected stages of which are mod-2 fed back to the input of the MLPSG, wherein the feedback satisfies a primitive, irreducible polynominal of degree N, the circuit to start a psueudorandom sequence is sending a starting pulse to the MLPSG if the MLPSG is in a state in which it does not produce pulse sequences, the pulse width and amplitude adjusting circuit is regulating the width, amplitude, shape and power of the pulses of the random sequence.
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Accused Products
Abstract
A randomized-clock circuit produces a random pulse train of predetermined sequence length and truncated exponential distribution of the gaps between pulses by multiplying a periodic clock signal with the output signal of a maximal length pseudorandom sequence generator which is clocked by the periodic clock signal. Control circuits monitor the maximal length pseudorandom pulse generator to start or stop random pulse sequences; random sequences are repeatable and a circuit to preset their starting point is provided. Cascading or connecting randomized-clock circuits in XOR, OR or AND gates is used to change the parameters of the exponential distribution function of the gaps. Pulse width and amplitude adjusting circuits allow interfacing of the randomized-clock circuit (a) with trigger inputs of medical and scientific pulse generators and (b) with electrodes connected to primates when the randomized-clock circuit is used as a nerve and/or muscle stimulator.
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Citations
9 Claims
- 1. A randomized-clock circuit comprising a maximal length pseudorandom sequence generator (MLPSG), a periodic circuit clock, a multiplier, a circuit to start a pseudorandom sequence and a pulse width and amplitude adjusting circuit, the multiplier, multiplying the output of the MLPSG with the output of the periodic circuit clock, is providing at its output a random pulse train of known sequence length and gap statistics with truncated exponential distribution, the MLPSG comprises an N-stage shift register, selected stages of which are mod-2 fed back to the input of the MLPSG, wherein the feedback satisfies a primitive, irreducible polynominal of degree N, the circuit to start a psueudorandom sequence is sending a starting pulse to the MLPSG if the MLPSG is in a state in which it does not produce pulse sequences, the pulse width and amplitude adjusting circuit is regulating the width, amplitude, shape and power of the pulses of the random sequence.
- 4. A cascaded randomized-clock circuit, wherein a randomized-clock circuit is the circuit clock for n, n=1, 2, . . . , cascaded clock randomizers, said randomized-clock circuit comprising a maximal length pseudorandom sequence generator (MLPSG), a periodic circuit clock, a multiplier, a circuit to start a pseudorandom sequence and a pulse width and amplitude adjusting circuit, the multiplier, multiplying the output of the MLPSG with the output of the periodic circuit clock, is providing at its output a random pulse train of known sequence length and gap statistics with truncated exponential distribution, the MLPSG comprises an N-stage shift register, selected stages of which are mod-2 fed back to the input of the MLPSG, wherein the feedback satisfied a primitive, irreducible polynomial of degree N, the circuit to start a pseudorandom sequence is sending a starting pulse to the MLPSG is in a state in which it does not produce pulse sequences, the pulse width and amplitude adjusting circuit is regulating the width, amplitude, shape and power of the pulses of the random sequence.
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7. A random pulse generator comprising k randomized-clock circuits with periodic clock frequencies fk =fk-1 +Δ
- fk, fk >
>
Δ
fk, where k=2, 3, . . . , and the randomized-clock circuit outputs are combined in one of a XOR, OR and AND gate, said randomized-clock circuit comprising a maximal length pseudorandom sequence generator (MLPSG), a periodic circuit clock, a multiplier, a circuit to start a pseudorandom sequence and a pulse width and amplitude adjusting circuit, the multiplier, multiplying the output of the MLPSG with the output of the periodic circuit clock, is providing at its output a random pulse train of known sequence length and gap statistics with truncated exponential distribution, the MLPSG comprises an N-stage shift register, selected stages of which are mod-2 fed back to the input of the MLPSG, wherein the feedback satisfies a primitive, irreducible polynomial of degree N, the circuit to start a pseudorandom sequence is sending a starting pulse to the MLPSG if the MLPSG is in a state in which it does not produce pulse sequences, the pulse width and amplitude adjusting circuit is regulating the width, amplitude, shape, and power of the pulses of the random sequence. - View Dependent Claims (8, 9)
- fk, fk >
Specification