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Randomized-clock circuit

  • US 4,571,556 A
  • Filed: 07/28/1983
  • Issued: 02/18/1986
  • Est. Priority Date: 07/28/1983
  • Status: Expired due to Fees
First Claim
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1. A randomized-clock circuit comprising a maximal length pseudorandom sequence generator (MLPSG), a periodic circuit clock, a multiplier, a circuit to start a pseudorandom sequence and a pulse width and amplitude adjusting circuit, the multiplier, multiplying the output of the MLPSG with the output of the periodic circuit clock, is providing at its output a random pulse train of known sequence length and gap statistics with truncated exponential distribution, the MLPSG comprises an N-stage shift register, selected stages of which are mod-2 fed back to the input of the MLPSG, wherein the feedback satisfies a primitive, irreducible polynominal of degree N, the circuit to start a psueudorandom sequence is sending a starting pulse to the MLPSG if the MLPSG is in a state in which it does not produce pulse sequences, the pulse width and amplitude adjusting circuit is regulating the width, amplitude, shape and power of the pulses of the random sequence.

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