Arithmetic operation apparatus using solar cells

• US 4,571,690 A
• Filed: 03/29/1983
• Issued: 02/18/1986
• Est. Priority Date: 03/30/1982
• Status: Expired due to Term

• Current Assignee: Tokyo Shibaura Denki Kabushiki Kaisha (Toshiba Corporation)
• Original Assignee: Tokyo Shibaura Denki Kabushiki Kaisha (Toshiba Corporation)
• Inventors: Munetsugu, Eiichi
• Primary Examiner(s): Chin, Gary
• Application Number:
  US06/480,003
• Time in Patent Office: 1,057 Days
• Field of Search: 364/483, 364/705, 364/707, 361/88, 361/90, 340/660, 340/661, 340/662, 340/663, 323/906, 323/221, 320/2, 354/484, 136/206, 136/291, 136/293
• US Class Current: 700/298
• CPC Class Codes: G06F 1/24 Resetting means
• CPC Class Codes: G06F 1/30 Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations for resetting only G06F1/24
• CPC Class Codes: Y10S 323/906 Solar cell systems

Abstract

Two different set voltages are respectively compared with a power source voltage. When the smaller set voltage which is close to a minimum operating voltage of an arithmetic circuit coincides with the power source voltage, a clock signal generator, and hence the arithmetic circuit are stopped. When the power source voltage increases to coincide with the larger set voltage after the clock signal generator is stopped, the clock signal generator and hence the arithmetic circuit are restarted.

Claims

1. An arithmetic operation apparatus using solar cells as a power source, comprising:

capacitor means, connected to said solar cells, for smoothing the power output of said solar cells;

arithmetic operating means, connected to said capacitor means to receive a voltage generated by said solar cells as a power source voltage, for executing various types of operations;

clock signal generating means for generating clock signals to be used as synchronization signals in said arithmetic operating means;

voltage comparator means for compairing said power source voltage with a first set voltage and with a second set voltage, the absolute value of said first set voltage being smaller than the absolute value of said second set voltage, said first set voltage being set to be close to a minimum value above which erroneous operation of said arithmetic operating means will not occur; and

controlling means for interrupting the generation of said clock signals by said clock signal generating means when said voltage comparator means determines a coincidence between said first set voltage and said power source voltage, and for restarting said clock signal generating means when said voltage comparator means determines a coincidence between said second set voltage and said power source voltage after a clock signal interruption.

2. An apparatus according to claim 1, wherein said voltage comparator means comprises:

a first voltage comparator for comparing the first set voltage with the power source voltage to produce a high-level logic signal when the power source voltage is greater than the first set voltage and to produce a low-level logic signal when the power source voltage coincides with the first set voltage; and

a second voltage comparator for comparing the second set voltage with the power source voltage to produce a low-level logic signal when the power source voltage is smaller than the second set voltage and to produce a high-level logic signal when the power source voltage coincides with the second set voltage.

3. An apparatus according to claim 1, wherein said controlling means comprises a flip-flop which is controlled in accordance with logic signals from said voltage comparator means.