Method of making vertical channel field controlled device employing a recessed gate structure

• US 4,571,815 A
• Filed: 09/12/1984
• Issued: 02/25/1986
• Est. Priority Date: 11/23/1981
• Status: Expired due to Term

• Current Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Original Assignee: General Electric Company
• Inventors: Baliga, Bantval J., Love, Robert P.
• Primary Examiner(s): Ozaki, George T.
• Application Number:
  US06/650,315
• Time in Patent Office: 531 Days
• Field of Search: 148/187, 29/571, 29/578, 29/580, 29/591
• US Class Current: 438/137
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 29/1066 Gate region of field-effect devices with PN junction gate
• CPC Class Codes: H01L 29/66363 Thyristors
• CPC Class Codes: H01L 29/66416 Static induction transistors [SIT] with an active layer made of a group 13/15 material H01L29/66454

Abstract

A vertical channel junction gate electric field controlled device (e.g., a field effect transistor or a field controlled thyristor) includes a semiconductor base region layer, and a plurality of grooves having vertical walls formed in the upper surface of the base region layer. Between the grooves on the upper surface of the base region layer but not extending to the grooves are upper electrode regions, for example, source electrode regions or cathode electrode regions. Formed in the groove bottoms and sidewalls are junction gate regions. Upper electrode terminal metallization is evaporated generally on the upper device layer, and gate terminal metallization is over the junction gate regions at the bottoms of the grooves. The disclosed structure thus has continuous metallization along the recessed gate regions for a low-resistance gate connection. The structure facilitates fabrication by methods, also disclosed, which avoid any critical photolithographic alignment steps in masking to define the locations of the source (or cathode) and gate regions, and avoid the need for any mask or mask alignment for metal definition when forming electrode metallization. As a result of the structure of the upper electrode and gate regions, it is not critical to avoid any metal deposition on the groove sidewalls.

Claims

1. A method of fabricating a vertical channel electric field controlled device having a recessed gate structure and being of the type including a semiconductor base region of one conductivity type and a gate region of opposite conductivity type, said method comprising:

providing a semiconductor wafer having a base layer of the one conductivity type;

forming a layer of silicon dioxide with a plurality of windows on one surface of the base layer, alternate windows defining the ultimate locations of upper electrode regions and gate regions;

forming an etchant barrier of silicon nitride patterned so as to cover the windows in the silicon dioxide layer defining the ultimate locations of gate regions, and to leave open the windows in the silicon dioxide layer defining the ultimate locations of upper electrode regions;

introducing into the base layer through the windows in the silicon dioxide layer defining the ultimate locations of upper electrode regions impurities appropriate to form upper electrode regions of the one conductivity type and of higher conductivity than the base region;

growing an oxide layer over the diffused upper electrode regions thinner than the oxide layer over the remainder of the base layer;

removing the silicon nitride barrier to expose the windows in the silicon dioxide layer defining the ultimate locations of gate regions;

forming substantially vertically-walled grooves beneath the gate region windows;

introducing into the sidewalls and bottoms of the grooves impurities appropriate to form gate regions of the opposite conductivity type;

removing the oxide layer over the upper electrode regions; and

evaporating metal onto the wafer surface to form metalized source terminals in ohmic contact with the upper electrode regions, and to form elongated metallized gate terminal fingers in ohmic contact with the gate regions at the bottoms of the grooves.

2. A method in accordance with claim 1, which further comprises deliberately undercutting the oxide layer surrounding the gate region windows when the vertically-walled grooves are formed.

3. A method in accordance with claim 1, which further comprises:

etching the base layer to form a recessed gate contact pad area at the same level as the bottoms of the grooves; and

evaporating metal onto the gate contact pad area to form a gate contact pad as a physical and electrical extension of the gate terminal fingers.

4. A method in accordance with claim 1, wherein the base layer provided is of N- conductivity type, the upper electrode regions formed are of N+ conductivity type, and the gate regions formed are of P+ conductivity type.

5. A method of fabricating a vertical channel junction gate electric field controlled device having a recessed gate structure and being of the type including a semiconductor base region of one conductivity type and a gate region of opposite conductivity type, said method comprising:

providing a semiconductor wafer having a base layer of the one conductivity type, and of crystallographic orientation selected to facilitate preferential etching;

forming a layer of silicon dioxide with a plurality of elongated windows on one surface of the base layer, alternate windows defining the ultimate locations of upper electrode regions and gate regions;

forming a barrier of silicon nitride patterned so as to cover the windows in the silicon dioxide layer defining the ultimate locations of gate regions, and to leave open the windows in the silicon dioxide layer defining the ultimate locations of the upper electrode regions;

introducing into the base layer through the windows in the silicon dioxide layer defining the ultimate locations of upper electrode regions impurities appropriate to form electrode regions of the one conductivity type and of higher conductivity than the base region;

growing an oxide layer over the diffused electrode regions thinner than the oxide layer over the remainder of the base layer;

removing the silicon nitride barrier to expose the windows in the silicon dioxide layer defining the ultimate locations of the gate regions;

preferentially etching the base layer to form substantially vertically-walled grooves beneath the gate region windows with undercutting of the oxide layer surrounding the gate region windows;

introducing into the sidewalls and bottoms of the grooves impurities appropriate to form gate regions of the opposite conductivity type;

removing the oxide layer over the upper electrode regions; and

evaporating metal onto the wafer surface to form metallized electrode terminals in ohmic contact with the upper electrode regions, and to form elongated metallized gate terminal fingers in ohmic contact with the gate regions at the bottoms of the grooves.

6. A method in accordance with claim 5, wherein the semiconductor base layer comprises silicon with a <

110>

crystallographic orientation and with a set of <

111>

planes at right angles to the <

110>

surface, and the parallel elongated windows are defined along the <

211>

direction.

7. A method in accordance with claim 5 which further comprises:

etching the base layer to form a recessed gate contact pad area at the same level as the bottoms of the grooves; and

evaporating metal onto the gate contact pad area to form a gate contact pad as a physical and electrical extension of the gate terminal fingers.