Control unit for model vehicles

• US 4,572,996 A
• Filed: 04/19/1984
• Issued: 02/25/1986
• Est. Priority Date: 04/22/1983
• Status: Expired due to Fees

• Current Assignee: Gebruder Marklin and CIE
• Original Assignee: Gebruder Marklin & CIE Gesellschaft Mit Beschrankter Haftung
• Inventors: Mayer, Roland, Hanschke, Christoph
• Primary Examiner(s): Shoop, Jr., William M.
• Assistant Examiner(s): Ip, Shik Luen Paul
• Application Number:
  US06/602,183
• Time in Patent Office: 677 Days
• Field of Search: 318/301, 318/317, 318/318, 318/341, 318/342, 318/343, 318/345 A, 318/345 E, 318/345 F, 318/39, 318/599, 318/16, 318/587, 318/600-608, 318/581, 466/455, 340/825.72, 340/825.56, 340/825.76, 340/825.63, 340/825.69, 180/167, 180/168, 455/162-164
• US Class Current: 388/809
• CPC Class Codes: A63H 19/24 Electric toy railways; Systems therefor
• CPC Class Codes: Y10S 388/904 Stored velocity profile
• CPC Class Codes: Y10S 388/912 Pulse or frequency counter

Abstract

A control unit for model vehicles, such as model railway trains, model automobiles, etc. For independent operation of several model vehicles on a common electric circuit, it is known to allocate to each model vehicle a receiver coded in relation with hardware and controlled according to a binary word consisting of an address part and a data part. Control units of this type, however, have the disadvantage that they cannot be operated on analog electric circuits. With the invention, a control unit is proposed which independently switches off the digital control logic in the case of a change of the model vehicle from a digital trackage to an analog trackage, and enables operation of the model vehicle via an amplitude-controlled or pulse width-controlled analog signal.

Claims

1. A control unit for model vehicles which are supplied with energy, for independent operation, via a common electric circuit, and which are selected by a transmitter which, via a line bus formed by the electric circuit, transmits to a receiver arranged in the model vehicle binary words consisting of an address part and a data part;

the receiver, which is coded in conformity with the address part, takes over the received data part in a register having parallel data outputs and transmits it to an analyzer which switches statuses, which correspond to the data, and control elements, which are arranged in the power circuit of the motor of the model vehicle;

the improvement comprises;

a counter having a reset imput, which is acted upon by reset pulses of constant frequency, and having a counting input, which is connected with said line bus in such a way that within a time window defined by two reset pulses which follow one another, the pulses of binary words received are counted in;

a storage having a data input which is set as a function of the count of said counter in such a way that below a given count of said counter said data input assumes a first logic status, and on and after said given count assumes a second logic status;

the logic status present at said data input is stored in said storage shortly before a following reset pulse; and

a first gate for time-limitedly operating, or for fully connecting through, in conformity with the statuses switched by said analyzer, said control elements as a function of the storage fill of said storage;

said storage being a D-flip-flop having a clock input at which is present a clock pulse which in terms of time is slightly in advance of said reset pulse;

said D-flip-flop having a Q output state; and

which includes as said first gate a first AND-gate for logically interconnecting said Q output state of said D-flip-flop with output signals of said analyzer;

said first AND-gate having an output which controls at least one of said control elements.

2. A control unit according to claim 1, which includes an intermediate storing flip-flop, which has a set input, and a Q output state which is connected with said data input of said storage;

and in which said counter is a binary counter, with the data output thereof having the highest decimal value being connected with said set input of said intermediate storing flip-flop.

3. A control unit according to claim 2, in which said intermediate storing flip-flip has a reset input, which is connected with said reset input of said counter.

4. A control unit according to claim 1, in which said storage is a D-flip-flop having a clock input at which is present a clock pulse which in terms of time is slightly in advance of said reset pulse.

5. A control unit according to claim 4, in which said D-flip-flop has a Q output state;

and which includes as said first gate a first AND-gate for logically interconnecting said Q output state of said D-flip-flop with output signals of said analyzer;

said first AND-gate has an output which controls at least one of said control elements.

6. A control unit for model vehicles which are supplied with energy, for independent operation, via a common electric circuit, and which are selected by a transmitter which, via a line bus formed by the electric ciruit, transmits to a receiver arranged in the model vehicle binary words consisting of an address part and a data part;

the receiver, which is coded in conformity with the address part, takes over the received data part in a register having parallel data outputs and transmits it to an analyzer which switches statuses, which correspond to the data, and control elements, which are arranged in the power circuit of the motor of the model vehicle;

the improvement comprises;

a counter having a reset input, which is acted upon by reset pulses of constant frequency, and having a counting input, which is connected with said line bus in such a way that within a time window defined by two reset pulses which follow one another, the pulses of binary words received are counted in;

a storage having a data input which is set as a function of the count of said counter in such a way that below a given count of said counter said data input assumes a first logic status, and on and after said given count assumes a second logic status;

the logic status present at said data input is stored in said storage shortly before a following reset pulse;

a first gate for time-limitedly operating, or for fully connecting through, in conformity with the statuses switched by said analyzer, said control elements as a function of the storage fill of said storage;

said storage being a D-flip-flop having a clock input at which is present a clock pulse which in terms of time is slightly in advance of said reset pulse; and

a first Schmitt-trigger, which has an inverted output signal and an input;

in which said D-flip-flop has a Q output state;

which includes a second AND-gate for logically interconnecting said Q output state of said D-flip-flop with said inverted output signal of said first Schmitt-trigger;

said second AND-gate having an output signal which controls at least one of said control elements;

which includes a parallel connection comprising a capacitor and a resistor; and

in which said input of said firt Schmitt-trigger is connected with the positive pole of the rectified voltage of said line bus, and, via said parallel connection, to ground.

7. A control unit for model vehicles which are supplied with energy, for independent operation, via a common electric circuit, and which are selected by transmitter which, via a line bus formed by the electric circuit, transmits to a receiver arranged in the model vehicle binary words consisting of an address part and a data part;

the receiver, which is coded in conformity with the address part, takes over the received data part in a register having parallel data outputs and transmits it to an analyzer which switches statuses, which correspond to the data, and control elements, which are arranged in the power circuit of the motor of the model vehicle;

the improvement comprises;

a counter having a reset input, which is acted upon by reset pulses of constant frequency, and having a counting input, which is connected with said line bus in such a way that within a time window defined by two reset pulses which follow one another, the pulses of binary words received are counted in;

a storage having a data input which is set as a function of the count of said counter in such a way that below a given count of said counter said data input assumes a first logic status, and on and after said given count assumes a second logic status;

the logic status present at said data input is stored in said storage shortly before a following reset pulse;

a first gate for time-limitedly operating, or for fully connecting through, in conformity with the statuses switched by said analyzer, said control elements as a function of the storage fill of said storage;

said storage being a D-flip-flop having a clock input at which is present a clock pulse which in terms of time is slightly in advance of said reset pulse; and

a flip-flop which is controlled as a driving direction storage and has a set input, a reset input, data input, Q and Q outputs, and a clock input;

which includes a logic control for directly controlling said set and reset inputs of said driving direction storage by two allocated statuses present at the data outputs of said receiver;

said driving direction storage is controllable independently of said set and reset inputs thereof in toggle operation, with said data input thereof being connected with one of said outputs thereof;

which includes a third AND-gate having an output and inputs, with said clock input of said driving direction storage being connected with said output of said third AND-gate;

in which said D-flip-flop is part of a digital/analog identification, and has a Q output state;

which includes two inverting Schmitt-triggers;

said inputs of said third AND-gate being connected on the one hand with said Q output state of said D-flip-flop, and on the other hand, via said two inverting Schmitt-triggers, with the rectified voltage of said line bus; and

which includes fourth and fifth gates, each of which has first and second inputs, with said Q and Q outputs of said driving direction storage each selecting one of said fourth and fifth gates at said first inputs thereof, with the pulses which control said control elements being present at said second inputs thereof.

8. A control unit according to claim 7, in which said two allocated statuses present at the data outputs of said receiver are digitally 0000 and 0001.

9. A control unit for model vehicles which are supplied with energy, for independent operation, via a common electric circuit, and which are selected by a transmitter which, via a line bus formed by the electric circuit, transmits to a receiver arranged in the model vehicle binary words consisting of an address part and a data part;

the receiver, which is coded in conformity with the address part, takes over the received data part in a register having parallel data outputs and transmits it to an analyzer which switches statuses, which correspond to the data, and control elements, which are arranged in the power circuit of the motor of the model vehicle;

the improvement comprises;

a counter having a reset input, which is acted upon by reset pulses of constant frequency, and having a counting input, which is connected with said line bus in such a way that within a time window defined by two reset pulses which follow one another, the pulses of binary words received are counted in;

a storage having a data input which is set as a function of the count of said counter in such a way that below a given count of said counter said data input assumes a first logic status, and on and after said given count assumes a second logic status;

the logic status present at said data input is stored in said storage shortly before a following reset pulse;

a first gate for time-limitedly operating, or for fully connecting through, in conformity with the statuses switched by said analyzer, said control elements as a function of the storage fill of said storage; and

a ring counter which counts up with impressed frequency;

which includes a flip-flop which is set by said ring counter before counting starts;

which includes a 4-bit comparator having an output signal which resets said flip-flop when the logic statuses of the data outputs of said receiver coincide with the logic statuses of the corresponding counting outputs of said ring counter; and

in which said flip-flop has a Q output state which emits the control pulses for said control elements.

10. A control unit according to claim 9, which includes a 4-bit AND-gate having inputs to which are connected the data outputs of said receiver;

said 4-bit AND-gate has an output signal which is fed as a control pulse to said control elements.

11. A control unit for model vehicles such as model railway trains, model automobiles and the like with features including the electrical motors of model vehicles supplied with energy via a common electric circuit, control switch elements comprising Darlington-transistors arranged in the electric circuit of the motor, said electric circuit being connected with a transmitter which transmits binary words via the electric circuit serving as a supply-conductor bus, with the binary words consisting of an address portion with a data portion, the binary words being transmitted by the transmitter via the electric circuit and being received in every model vehicle by a receiver module (decoder) connected with the electric circuit, each receiver module (decoder) being coded for a particular address of its own, such that if the coded address of a receiver module (decoder) of one model vehicle agrees or coincides with the address portion of a transmitted binary word, accordingly the data portion received upon the address portion is taken over in a register in the receiver module (decoder), said register being connected with an evaluation circuit analyzer which produces control signals corresponding to the data portion and actuates the switch elements comprising Darlington-transistors via grating gate (output) and accordingly being operative to regulate and control the speed of the motor, the improvements in combination therewith additionally comprising:

a digital/analog identification unit including a counter of which the reset input has reset impulses of fixed frequency applied thereto and of which the counter input is connected with the electric circuit/supply-conductor bus;

said counter serving to count all impulses of received binary words within a time interval (window) determined by two sequential reset impulses following one upon another;

above a predetermined counter position of the counter, the data input of a storage flip-flop being set at a first logic condition (logic

     1);

below this prescribed counter position of the counter, the data input of the storage flip-flop being set at a second logic condition (logic

     0), the condition (0 or

     1) applicable at the data input being stored away in the storage flip-flop shortly before a subsequently following reset impulse;

the storage content being associated and tied together with the control signals of an analyzer evaluation circuit via the grating gate, whereby the output of the grating gate actuates a switch element or Darlington-transistor located in the power circuit;

with the first logic condition (logic

     1) of the storage or flip-flop, the grating gate being opened for the control signals of the analyzer evaluation circuit and the switch elements being actuated by the control signals of the analyzer evaluation circuit (digital operation); and

in the second logic condition (logic

     0) of the storage flip-flop, the grating gate being blocked and closed for the control signals of the analyzer evaluation circuit and the switch elements comprising Darlington transistors which are connected-through in such a manner that the unchanged voltage amplitude of the current circuit is applied at the motor.