Switched capacitor filter utilizing a differential input and output circuit and method

• US 4,574,250 A
• Filed: 10/13/1981
• Issued: 03/04/1986
• Est. Priority Date: 10/13/1981
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Senderowicz, Daniel
• Primary Examiner(s): LaRoche, Eugene R.
• Assistant Examiner(s): Mottola, Steven J.
• Application Number:
  US06/311,144
• Time in Patent Office: 1,603 Days
• Field of Search: 330/51, 330/107, 330/109, 330/252, 330/253, 330/258, 330/307, 328/151
• US Class Current: 330/258
• CPC Class Codes: H03F 2200/372 Noise reduction and elimination in amplifier
• CPC Class Codes: H03F 3/005 using switched capacitors, e.g. dynamic amplifiers; using switched capacitors as resistors in differential amplifiers H03F3/45 takes precedence
• CPC Class Codes: H03F 3/45479 characterised by the way of common mode signal rejection
• CPC Class Codes: H03H 19/004 Switched capacitor networks

Abstract

The invention is a differential amplifier, having internal common mode feedback and correction between a first stage and a second stage of the differential amplifier, which is used as a switched capacitor integrator in a switch capacitor filter in combination with an encoder and decoder which is fully differential throughout the circuit.

Claims

1. In an integrated circuit, a differential integration circuit having first and second inputs comprising:

a balanced output operational amplifier having a negative input terminal and a positive input terminal;

a first balanced switched capacitor sampler coupled to said first and second inputs said first sampler also coupled to said amplifier negative and positive input terminals;

a second balanced switched capacitor sampler;

a positive voltage output of said operational amplifier coupled to said second sampler and fed back to said amplifier negative input terminal through a first capacitor;

a negative voltage output of said operational amplifier coupled to said second sampler and fed back to said amplifier positive input terminal through a second capacitor;

a center voltage output of said operational amplifier equal to the difference between said positive voltage output and said negative voltage output, said center voltage output coupled to said second sampler;

whereby differential signals may be transferred through said circuit such that said circuit has improved power supply rejection and high signal to noise ratio.

2. The circuit of claim 1 wherein said balanced output operational amplifier includes a cascade of two differential amplifiers, each with active loads.

3. The circuit of claim 2 including a common mode feedback path between said two cascaded differential amplifiers.