Multiple access system and method

• US 4,574,378 A
• Filed: 06/10/1983
• Issued: 03/04/1986
• Est. Priority Date: 06/14/1982
• Status: Expired due to Term

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Kobayashi, Kazutomo
• Primary Examiner(s): NOT, DEFINED
• Assistant Examiner(s): Rokoff, Kenneth I.
• Application Number:
  US06/503,264
• Time in Patent Office: 998 Days
• Field of Search: 370/85, 370/93, 370/94, 370/95, 370/104, 340/825.5
• US Class Current: 370/348
• CPC Class Codes: H04B 7/18539 Arrangements for managing radio, resources, i.e. for establishing or releasing a connection
• CPC Class Codes: H04B 7/212 Time-division multiple access [TDMA]
• CPC Class Codes: H04L 1/18 Automatic repetition systems, e.g. Van Duuren systems
• CPC Class Codes: H04W 74/08 Non-scheduled access, e.g. ALOHA hybrid access H04W74/02
• CPC Class Codes: Y10S 370/913 Wireless or radio

Abstract

In a multiple access system for performing packet communication involving sharing of a single communication medium by a plurality of users, the single communication medium is divided into a plurality of channels. Each user monitors the condition of each channel, and probability of packet transmission to each channel is controlled in accordance with a monitored result.

Claims

1. A multiple access system for performing packet communication involving the sharing of a single communication medium by a plurality of users through a plurality of channels such that each user monitors the state of each channel and the probability of packet transmission is controlled in accordance with the monitored results comprising:

an interface section for linking data together as a packet;

a modem section for modulating/demodulating a packet, said modem section including

a modulator for modulating the packet;

a demodulator for demodulating a modulated packet to generate a demodulated signal; and

a slot sync signal detector for receiving the demodulated signal to extract the slot sync signal constantly propagated along the channel;

a carrier detector for detecting whether or not the channel is being used and for generating an empty or a busy signal;

a network control section for performing access control, said network control section including

a collision detector for detecting a transmitting packet and a delayed receiving packet so as to detect a collision of the transmitting packet with another transmitting packet, said collision detector generating a success signal when the transmitting packet and the delayed receiving packet coincide with each other and a collision signal when the transmitting packet and the delayed receiving packet do not coincide,

a retransmitter for retransmitting a packet identical with the transmitting packet when the transmitting packet collides with said delayed receiving packet, and

a control circuit for receiving a slot sync pulse, a busy or empty signal, a success or collision signal, and a packet arrival pulse, and for generating a control signal to control packet transmission; and

an RF section connected to said modem section for converting an IF signal to a high frequency transmission signal and vice versa.

2. A system according to claim 1, wherein said network control section further includes:

a buffer for supplying the packet arrival pulse to said control circuit every time said buffer receives the packet;

a gate circuit which is turned on in response to the control signal supplied from said control circuit thereto so as to pass the packet therethrough;

a delay circuit for delaying the packet from said gate circuit and for supplying a delayed packet to said retransmitter and said collision detector; and

an address filter for receiving only the packet destined therefore and supplying the packet to said interface section.

3. A system according to claim 1 wherein said control circuit comprises:

a memory for storing parameter data the number of which corresponds to the number of the channels;

a counter for counting the slot sync pulse in units of one frame, and subtracting the number of slots corresponding to a transmission delay time from count data thereof so as to obtain subtracted data;

a selector for receiving the subtracted data and the count data and for reading out parameter data corresponding to the subtracted data and the count data;

an arithmetic operation unit for receiving the parameter data corresponding to the subtracted data, updating the parameter data, and supplying updated parameter data to said memory; and

a pattern generator for receiving the parameter data corresponding to the count data and generating the control signal using as a probability the updated parameter data from said selector, thereby opening said gate circuit in accordance with said probability.

4. A system according to claim 1, wherein said control circuit comprises:

a first memory for storing parameter data the number of which corresponds to the number of the channels;

a second memory for storing single parameter data for controlling a sequence flow;

a counter for counting the slot sync pulse in units of one frame, subtracting a number of slots corresponding to a transmission delay time from count data thereof so as to obtain subtracted data;

a first selector for receiving the subtracted data and the count data and reading out parameter data corresponding to the subtracted data and the count data;

a first arithmetic operation unit for receiving the parameter data corresponding to the subtracted data, updating the parameter data, and supplying updated parameter data to said first memory;

a second selector for reading out the single parameter data from said second memory;

a second arithmetic operation unit for receiving and updating the single parameter data, thereby restoring updated single parameter data in said second memory;

a multiplier for multiplying the updated subtracted parameter data from said first selector by the updated single parameter data from said second selector; and

a pattern generator for receiving multiplied parameter data from said multiplier and generating the control signal using as a probability the multiplied parameter data from said multiplier, thereby opening said gate from said multiplier, thereby opening said gate circuit in accordance with said probability.

5. A system according to claim 3 or 4, wherein said arithmetic operation unit comprises:

a function generator for generating a function value δ

(δ

=1 under a first condition that one of the empty and success signals is detected;

δ

=-1 under a second condition excluding the first condition); and

a first arithmetic logic circuit for receiving the function value δ

so as to perform an operation P_l ←

P_l +α

δ

where l=1 . . . L, L being the number of channels, 0≦

P_l ≦

1, and α

is a small positive number.

6. A system according to claim 5 further comprising:

a second arithmetic operation circuit for performing an operation λ

←

λ

-β

(Σ

P_l -1) where λ

is a Lagrangian constant, 0≦

λ

, and β

is a small positive number; and

a third arithmetic operation circuit for computing the Lagrangian constant λ

in accordance with λ

←

min (λ

,λ

₀) for λ

₀ ≲

1,

whereby said first arithmetic operation circuit is caused to perform an operation P_l ←

P_l +α

(δ

+λ

).

7. A system according to claim 6 further comprising an averaging circuit for producing σ

L where σ

is an average of the number of input packet arrival pulses, whereby said second arithmetic operation circuit performs an operation

space="preserve" listing-type="equation">λ

←

λ

-β

(Σ

P.sub.l -σ

L)

8. A multiple access system for performing packet communication involving the sharing of a single communication medium by a plurality of users through a plurality of channels such that each user monitors the state of each channel and the probability of packet transmission is controlled in accordance with the monitored results comprising:

an interface section for linking data together as a packet;

a modem section for modulating/demodulating a packet, said modem section including

a modulator for modulating the packet;

a demodulator for demodulating a modulated packet to generate a demodulated signal; and

a slot sync signal detector for receiving the demodulated signal to extract the slot sync signal constantly propagated along the channel;

a carrier detector for detecting whether or not the channel is being used and for generating an empty or a busy signal;

a network control section for performing access control, said network control section including

a collision detector for detecting a transmitting packet and a delayed receiving packet so as to detect a collision of the transmitting packet with another transmitting packet, said collision detector generating a success signal when the transmitting packet and the delayed receiving packet coincide with each other and a collision signal when the transmitting packet and the delayed receiving packet do not coincide;

a channel collision detector for detecting whether a collision occurs between received packets, said control circuit receiving a collision signal from said channel collision detector;

a retransmitter for retransmitting a packet identical with the transmitting packet when the transmitting packet collides with said delayed receiving packet, and

a control circuit for receiving a slot sync pulse, a busy or empty signal, a success or collision signal, and a packet arrival pulse, and for generating a control signal to control packet transmission; and

an RF section connected to said modem section for converting an IF signal to a high frequency transmission signal and vice versa.

9. A system according to claim 8, wherein said network control section further includes:

a buffer for supplying the packet arrival pulse to said control circuit every time said buffer receives the packet;

a gate circuit which is turned on in response to the control signal supplied from said control circuit so as to pass the packet therethrough;

a delay circuit for delaying the packet from said gate circuit and for supplying a delayed packet to said retransmitter and said collision detector; and

an address filter for receiving only the packet destined thereto and supplying the packet to said interface section.

10. A system according to claim 8, wherein said control circuit comprises:

a first memory for storing parameter data the number of which corresponds to the number of the channels;

a second memory for storing single parameter data for controlling a sequence flow;

a counter for counting the slot sync pulse in units of one frame, subtracting a number of slots corresponding to a transmission delay time from count data thereof so as to obtain subtracted data;

a first selector for receiving the subtracted data and the count data and reading out parameter data corresponding to the subtracted data and the count data;

a first arithmetic operation unit for receiving the parameter data corresponding to the subtracted data, updating the parameter data, and supplying updated parameter data to said first memory;

a second selector for reading out the single parameter data from said second memory;

a second arithmetic operation unit for receiving and updating the single parameter data, thereby restoring updated single parameter data in said second memory;

a multiplier for multiplying the updated subtracted parameter data from said first selector by the updated single parameter data from said second selector; and

a pattern generator for receiving multiplied parameter data from said multiplier and generating the control signal using as a probability the multiplied parameter data from said multiplier, thereby opening said gate circuit in accordance with the probability.

11. A system according to claim 4 or 10, wherein said second arithmetic operation circuit comprises:

a function generator for generating a function value ξ

(ξ

=-1 under a first condition that the collision signal is detected;

ξ

=ξ

₀ >

0 under a second condition excluding the first condition); and

an arithmetic logic circuit for receiving and updating the function value ξ

in accordance with the updated single parameter data so as to perform an operation P←

P+rξ

(where P is the single parameter data 0≦

P≦

1, ξ

is the function value, and r is a small positive number.