Circuit for establishing accurate sample timing

• US 4,575,682 A
• Filed: 08/30/1984
• Issued: 03/11/1986
• Est. Priority Date: 09/01/1983
• Status: Expired due to Term

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Hirosaki, Botaro, Aoyagi, Hidehito
• Primary Examiner(s): LaRoche, Eugene R.
• Assistant Examiner(s): MIS, DAVID C
• Application Number:
  US06/645,684
• Time in Patent Office: 558 Days
• Field of Search: 329/50, 329/110, 329/122, 329/135, 375/39, 375/80, 375/81, 375/94, 375/118, 375/120, 455/214, 455/337
• US Class Current: 329/308
• CPC Class Codes: H04L 2025/03414 Multicarrier
• CPC Class Codes: H04L 25/03133 with a non-recursive structure H04L25/03127 takes precedence
• CPC Class Codes: H04L 27/2657 Carrier synchronisation
• CPC Class Codes: H04L 27/2662 Symbol synchronisation
• CPC Class Codes: H04L 27/2679 Decision-aided
• CPC Class Codes: H04L 27/38 Demodulator circuits; Receiver circuits

Abstract

In order to establish accurate sample timing in a digital demodulator which forms part of an orthogonally multiplexed parallel data transmission system, two second-order PLLs are arranged after a demodulating section of the digital demodulator so as to receive baseband signals of corresponding pilot channels. The two second-order PLLs each includes an integrator. These integrators apply the outputs thereof to a subtracter which applies the subtraction result to a voltage-controlled oscillator in order to establish the accurate sample timing.

Claims

1. A circuit for establishing accurate sample timing by correcting sampling frequency offsets and sampling phase offsets, said circuit forming part of a demodulator for an orthogonally multiplexed parallel data transmission system, said demodulator including a demodulating section which receives the orthogonally multiplexed parallel data to recover baseband signals of corresponding parallel channels which consist of data and pilot channels, said circuit comprising:

a first second-order PLL which includes a first integrator, said first second-order PLL being arranged after said demodulating section so as to receive a recovered baseband signal of a first pilot channel;

a second second-order PLL which includes a second integrator, said second second-order PLL being arranged after said demodulating section so as to receive a recovered baseband signal of a second pilot channel;

a subtracter which is supplied with the outputs of said first and second integrators and which produces the subtraction result as sampling frequency offset information; and

a voltage-controlled oscillator which receives the output of said subtracter so as to establish the accurate sample timing.

2. A circuit as claimed in claim 1, wherein said first and second pilot channels are the end channels of said parallel channels.

3. A circuit as claimed in claim 1, further including;

a plurality of automatic equalizers which are allotted to the data channels inclusive of the center channel of said parallel channels, said plurality of automatic equalizers producing sampling phase offset information; and

an adder which adds said sampling frequency offset information and said sampling phase offset information, said adder applying the output thereof to said voltage-controlled oscillator.

4. A circuit as claimed in claim 3, wherein said first and second pilot channels are the end channels of said parallel channels.

5. A circuit for establishing accurate sample timing by correcting sampling frequency offsets and sampling phase offsets, said circuit forming part of a demodulator for an orthogonally multiplexed parallel data transmission system, said demodulator including a demodulating section which receives the orthogonally multiplexed parallel data to recover baseband signals of corresponding parallel channels which consist of data and pilot channels, said circuit comprising:

a first second-order PLL which includes a first integrator, said first second-order PLL being arranged after said demodulating section so as to receive a recovered baseband signal of a first pilot channel;

a second second-order PLL which includes a second integrator, said second second-order PLL being arranged after said demodulating section so as to receive a recovered baseband signal of a second pilot channel;

a subtracter which is supplied with the outputs of said first and second integrators and which produces the subtraction result as sampling frequency offset information;

a plurality of automatic equalizers which are allotted to the data channels inclusive of the center channel of said parallel channels, said plurality of automatic equalizers producing sampling phase offset information;

an adder which adds said sampling frequency offset information and said sampling phase offset information; and

a voltage-controlled oscillator which receives the output of said adder so as to establish the accurate sample timing.

6. A circuit as claimed in claim 5, wherein said first and second pilot channels are the end channels of said parallel channels.

7. A circuit for establishing accurate sample timing by correcting sampling frequency offsets and sampling phase offsets, said circuit forming part of a demodulator for an orthogonally multiplexed parallel data transmission system, said demodulator including a demodulating section which receives the orthogonally multiplexed parallel data to recover baseband signals of corresponding parallel channels which consist of data and pilot channels, said circuit comprising:

a first second-order PLL which includes a first integrator, said first second-order PLL being arranged after said demodulating section so as to receive a recovered baseband signal of a first pilot channel;

a second second-order PLL which includes a second integrator, said second second-order PLL being arranged after said demodulating section so as to receive a recovered baseband signal of a second pilot channel;

a subtracter which is supplied with the outputs of said first and second integrators and which produces the subtraction result as sampling frequency offset information;

a plurality of automatic equalizers which are allotted to the data channels inclusive of the center channel of said parallel channels, said plurality of automatic equalizers producing sampling phase offset information;

a voltage-controlled oscillator which is adapted to control the sample timing;

a selector which allows said sampling frequency offset information to be applied to said voltage-controlled oscillator during a predetermined period after the system is initially operated, and which allows said sampling phase offset information to be applied to said voltage-controlled oscillator after said predetermined period elapses.

8. A circuit as claimed in claim 7, wherein said first and second pilot channels are the end channels of said parallel channels.

9. A circuit for establishing accurate sample timing by correcting sampling frequency offsets and sampling phase offsets, said circuit forming part of a demodulator for an orthogonally multiplexed parallel data transmission system, said demodulator including a demodulating section which receives the orthogonally multiplexed parallel data to recover baseband signals of corresponding parallel channels which consist of data and pilot channels, said circuit comprising:

a first second-order PLL which includes a first integrator, said first second-order PLL being arranged after said demodulating section so as to receive a recovered baseband signal of a first pilot channel;

a second second-order PLL which includes a second integrator, said second second-order PLL being arranged after said demodulating section so as to receive a recovered baseband signal of a second pilot channel;

a subtracter which is supplied with the outputs of said first and second integrators and which produces the subtraction result as sampling frequency offset information;

a plurality of automatic equalizers which are allotted to the data channels inclusive of the center channel of said parallel channels, said plurality of automatic equalizers producing sampling phase offset information;

a voltage-controlled oscillator which is adapted to control the sample timing;

a detector for detecting the absolute value of said sampling frequency offset; and

a selector which allows said sampling frequency offset information to be applied to said voltage-controlled oscillator when said detector detects the absolute value in excess of a predetermined value, and which allows said sampling phase offset information to be applied to said voltage-controlled oscillator when the absolute value detected by said detector is less than the predetermined value.

10. A circuit as claimed in claim 9, wherein said first and second pilot channels are the end channels of said parallel channels.