Flat panel display and method of manufacture

• US 4,577,133 A
• Filed: 10/27/1983
• Issued: 03/18/1986
• Est. Priority Date: 10/27/1983
• Status: Expired due to Fees

• Current Assignee: Wilson, Ronald E.
• Original Assignee: Wilson, Ronald E.
• Inventors: Wilson, Ronald E.
• Primary Examiner(s): Kellogg, Arthur
• Application Number:
  US06/546,103
• Time in Patent Office: 873 Days
• Field of Search: 445/24, 445/47, 445/49, 445/52, 313/422, 313/103 CM, 313/105 CM
• US Class Current: 313/103.0CM
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01J 2201/3125 Metal-insulator-Metal [MIM] emission type cathodes
• CPC Class Codes: H01J 31/127 using large area or array sources, i.e. essentially a source for each pixel group

Abstract

A flat panel display for video and/or information display including a geometric array of individually energizable, low energy electron emitters in combination with an array of continuous channel electron multipliers for amplifying and directing the electron outputs of the emitters onto a phosphor screen to emit visible light.

Claims

1. A flat panel display which has an overall resolution of up to 284,000 pixels per sqare inch, said display including means for generating a low energy flow of electrons, said means including low power selection devices for gating the electron flow, said devices being energized intermittently in response to electrical signals of from 2 to 20 volts, multiplying means having a constant bias voltage for multiplying the magnitude of the electron flow, and a phospher screen for receiving the gated electron flow, the means for generating and the multiplying means and the screen being assembled in close proximity in a two-dimensional array and vacuum sealed with the multiplying means sandwiched between the means for generating and the screen.

2. A flat panel display as defined in claim 1 in which the multiplying means is an array of continuous channel electron multipliers.

3. A flat panel display as defined in claim 2 in which the means for generating is of the cold cathode type and includes an orthogonal array of conductors separated by a dielectric.

4. A flat panel display as defined in claim 3 in which the means for generating includes a matrix of rows and columns of conductors with a dielectric there-between.

5. A flat panel display as defined in claim 4 in which the rows and columns are individually selectable to create a positive potential there-between, and each crossover point of a row and a column forms an electron emitter.

6. A flat panel display as defined in claim 5 in which the multiplying means includes a flat plate with a multiplicity of microscopic holes extending therethrough, the material of the plate forming the walls of the holes having a secondary surface emission characteristic.

7. A flat panel display as defined in claim 6 in which the holes define continuous channel electron multipliers and are aligned with the crossover points of the emitter, and there is one continuous channel electron multiplier and one crossover point for each picture element on the screen.

8. A flat panel display as defined in claim 7 in which the phosphor screen includes a glass plate, and the emitter matrix is supported on a substrate, the glass plate and the substrate forming the front and rear surfaces respectively of the panel.

9. A flat panel display as defined in claim 8 in which the electron multiplier includes a flat plate of glass having a composition of approximately 50% lead oxide, approximately 40% silicon dioxide, and approximately 10% alkali oxides, with the holes having an aspect ratio of diameter-to-length of approximately 1 to 20, said plate of glass having a semi-conductive surface produced by baking in a hydrogen atmosphere.

10. A flat panel display as defined in claim 9 in which the electron multiplier includes a layer of conductive metal adhered to the upper and lower surfaces of the plate of glass.

11. A flat panel display as defined in claim 2 in which the electron multiplier is spaced a small distance from the low energy emitter.

12. A flat panel display as defined in claim 11 in which the space between the electron multiplier and the low energy emitter is a vacuum.

13. A flat panel display as defined in claim 11 in which the space between the electron multiplier and the low energy emitter is filled with a dielectric.

14. A flat panel display as defined in claim 13 in which the electron multiplier and the low energy emitter are formed as a unit.

15. For use in a high resolution flat panel display, an electron multiplier comprising a flat plate with microscopic holes extending from one flat surface to the other, the spacing between adjacent holes being microscopic to permit a hole density of up to 284,000 holes per square inch, the diamter-to-length aspect of the holes being on the order of 1 to 20, the axes of the holes extending at an acute angle to the flat surfaces, and a thin metallic electrode adhered to and covering each flat surface of the plate.

16. An electron multiplier as defined in claim 15 in which the material of the plate has a secondary surface emission characteristic.

17. An electron multiplier as defined in claim 15 in which the flat plate is laminated of alternate layers of dielectric and thin sheets of conductive metal, with holes in each layer aligned to form a channel of segments joined by thin metallic electrodes.

18. An electron multiplier as defined in claim 17 in which means is provided for connecting a bias voltage across the plate in progressive increments between the metal sheets.

19. For use in a high resolution flat panel display, an electron emitter-amplifier unit comprising a sheet of dielectric material with an array of tunnel emission devices on one surface and an array of continuous channel multipliers on the opposite surface, the devices in said array being separated by uniform microscopic spaces to permit an array density of up to 284,000 devices per square inch.

20. An electron emitter-amplifier unit as defined in claim 19 in which the tunnel emission devices include an orthogonal array of conductors separated by a thin layer of dielectric.

21. An electron emitter-amplifier unit as defined in claim 19 in which the emission devices include a matrix of rows and columns of conductors with a thin layer of dielectric therebetween, and each crossover point of a row and a column forms an electron emitter.

22. An electron emitter-amplifier unit as defined in claim 21 in which each continuous channel multiplier is aligned with a crossover point.

23. An electron emitter-amplifier unit as defined in claim 22 in which the array of multipliers includes a flat plate with a layer of conductive metal adhered to both surfaces thereof, and microscopic holes extending through the flat plate and both metal layers and the dielectric sheet.

24. An electron emitter-amplifier unit as defined in claim 23 which includes means for connecting a bias voltage across the flat plate, and in which the rows and columns are individually selectable to create a positive potential therebetween.

25. An electron emitter-amplifier unit as defined in claim 24 which includes a glass substrate adhered to the tunnel emission devices to support and protect the unit.

26. A method of making an electron multiplier for a high resolution flat panel display which includes the steps of etching a multiplicity of microscopic holes having a diameter-to-length aspect on the order of 1 to 20 through at least one flat plate in a closely spaced two-dimensional array in which the holes are separated by uniform microscopic spaces to permit a hole density of up to 284,000 holes per square inch, and depositing a thin layer of conductive metal on each flat surface of the plate.

27. A method of making an electron multiplier as defined in claim 26 which includes

treating the material of the flat plate to make it semi-conductive.

28. A method of making an electron multiplier as defined in claim 26 which includes

superposing a plurality of the flat plates with the holes in alignment, and

adhering thin sheets of conductive metal between adjacent plates to form a laminated structure of alternating plates and sheets.