Digital multi-customer data interface
First Claim
1. A digital customer interface arrangement for communicating packets of data between a plurality of customer lines and a packet switch and comprisingmeans responsive to a receipt of serial bit signals for a plurality of customer lines for serially time multiplexing said bit signals,means responsive to a receipt of the time multiplexed bit signals for assembling individual byte signals for each one of said lines,means cooperating with said assembling means and controlled by the assembled byte signals for generating individual packets of data signals for each one of said lines,means for storing each generated packet of signals,means responsive to a receipt of customer line status bit signals from said time multiplexing means for control buffering said status bit signals for each of said lines, andmeans controlled with said buffered status bit signals and by said generating means for controlling a reading of the stored packets of signals from said storing means for transmission to said packet switch.
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Accused Products
Abstract
A communication method and digital multi-customer data interface for interconnecting a number of customer terminals to a main packet switching network of a local area data transport system that provides data communication services such as interactive video text service between data service vendors and customers. The digital multi-customer interface utilizes a main processor, control circuit, and multi-customer protocol controller to implement the protocol functions for the communication of packets and control information over individual serial transmission paths. The multi-customer protocol controller comprises a control processor and a formatter circuit for synchronously communicating packets for a plurality of customer terminals via customer line units and customer lines. The control processor performs byte-to-packet and packet-to-byte functions between the main processor and the formatter circuit. The formatter circuit is shared in common by all of the customer lines and performs the functions of assembling and disassembling data bytes from and to individual data bit signals, performing error cyclic redundancy checks and generations, performing flag recognition and generations, and performing bit stuffing and unstuffing. The control circuit handles communication of all control and status information between the main processor and the customer line units. The control buffer periodically transmits the control information received from the main processor to all of the customer units and receives back from them status information which is stored for later use by the main processor.
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Citations
40 Claims
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1. A digital customer interface arrangement for communicating packets of data between a plurality of customer lines and a packet switch and comprising
means responsive to a receipt of serial bit signals for a plurality of customer lines for serially time multiplexing said bit signals, means responsive to a receipt of the time multiplexed bit signals for assembling individual byte signals for each one of said lines, means cooperating with said assembling means and controlled by the assembled byte signals for generating individual packets of data signals for each one of said lines, means for storing each generated packet of signals, means responsive to a receipt of customer line status bit signals from said time multiplexing means for control buffering said status bit signals for each of said lines, and means controlled with said buffered status bit signals and by said generating means for controlling a reading of the stored packets of signals from said storing means for transmission to said packet switch.
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13. A digital interface system for communicating packets of information among a plurality of customer lines and a packet switch comprising
plural groups of customer line circuits with each line circuit connected to an individual customer line; -
a plurality of group distributor circuits, each said distributor circuit being connected to an individual group of said plural groups of line circuits for serially time multiplexing serial bit signals received therefrom; means cooperating with each of said distributor circuit for formatting said time multiplex bit signals into individual byte signals for each one of said lines; first program controlled processor means cooperating with said formatting means and controlled by said individual byte signals for generating individual packets of signals for each one of said lines; a common memory for storing each generated packet of signals; means responsive to a receipt of status bit signals from said group distributor circuits for control buffering said status bit signals for each of said lines; and second program controlled processor means controlled by said first processor means and said buffered status bit signals for controlling a reading of said stored packets of signals from said common memory for transmission to said packet switch. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22, 23)
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24. A digital customer interface for communicating synchronous packet data between a plurality of data customer terminals connected to said digital customer interface by a plurality of low-speed transmission links and a packet switching system connected to said digital customer interface via a high-speed transmission link, said digital customer interface comprising
a plurality of line circuits for serially receiving bit signals of packets of signals from said low-speed transmission links; -
data distribution means responsive to said received bit signals for serially time multiplexing said bit signals; means responsive to the time multiplexed bit signals for forming said time multiplexed bit signals into individual partially formed bytes of bit signals with each byte being individual to one of said line circuits; means for generating a byte done signal in response to a formatting of each byte of bit signals; first processor means responsive to a receipt of said byte done signal and a first set of program instructions for assembling each one of the formatted bytes into an individual one of a plurality of packets of signals associated with each one of said line circuits and being further responsive to a second set of instructions for generating a packet completion signal upon said each one of said packets of signals being assembled; and second processor means responsive to said packet completion signal for executing protocol operations to assemble said each one of said packets of signals into a frame for transmission on said high-speed transmission link. - View Dependent Claims (25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38)
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39. A method for communicating packets of signals between a plurality of customer lines and a packet switch by utilizing a digital customer interface having a main processor and a multiple-customer protocol controller comprising a data distributor circuit, a formatter circuit connectable to each of said lines by an individual one of a plurality of line circuits, formatter processor, and a control buffer circuit, said method comprising the steps of serially time multiplexing bit signals received from said customer lines by said data distributor circuit;
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generating individual byte signals for each one of said lines by said formatter circuit upon receipt of said time multiplexed bit signals; assembling packets of signals and control signals for each one of said lines in response to assembled byte signals by said formatter processor; storing each generated packet of signals for use by said main processor; transferring of status signals from each one of said line circuits to said main processor by said data distributor circuit and said control buffer circuit;
saidreading said stored packets of signals for transmission to said packet switch by said main processor in response to said control signals and said status signals. - View Dependent Claims (40)
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Specification